The 65nm process offers cost-effective benefits superior to the 90nm node. It features two times the 90nm gate density and boasts a speed improvement of between 30 to 50 percent. The 65nm process also provides the smallest SRAM cell and reduces power with a multiple Vt architecture and other process innovation.

TSMC's 65nm logic family includes general purpose (GP), low power (LP) and LPG options. Each process supports low, standard and high Vt options. Operating voltages range from 0.9V to 1.26V. I/O voltages include 1.8V, 2.5V and 3.3V (5V tolerant). Raw gate density is around 854 Kgate/mm2, based on TSMC's standard cell library. SRAM cells range from 0.499μm2 (6T) to 1.158μm2 (8T/10T).

The 65nm process provides a combination of general purpose (G) and low power (LP) core transistors together with a 2.5V I/O transistor as a Triple Gate Oxide (LPG) process for optimizing speed, power, and leakage for wireless/consumer applications.