Reference Flow Release 4.0
Addresses Nanometer Design Challenges with Foundry Industry's
First Dual-Track Reference Flow
This
is the industry's first complete design flow that responds specifically
to nanometer design challenges and features dual physical implementation
tracks built around commercial EDA tools primarily from Synopsys,
Inc. and Cadence Design Systems. Reference Flow 4.0 provides
IC design teams with the flexibility to tap into TSMC's recommended
design methodologies independent of tool preferences, while
directly addressing technical challenges related to designing
at 0.13 micron and 90-nanometers. And, for the first time, Reference
Flow 5.0 creates engineering collaboration across the entire
design chain, including chip and package design.
Proven Record of Quality Delivery
TSMC offered foundry industry’s
very first Reference Flow in April 2001. After two years and
three major releases of TSMC Reference Flow, reference flow
has turned into a standard design service offering in the foundry
industry with several other foundries starting their own reference
flow efforts only recently. TSMC is fully committed to proactively
anticipating and addressing new design implementation challenges.
The four consecutive quality deliveries of TSMC Reference Flow
continue to help the customers address their different design
implementation needs in different technology nodes and different
design characteristics.
Take Full Advantage of TSMC's
Nanometer Technologies
Along with the evolution of process
technologies, TSMC has anticipated the design challenges for
each new process technology generation and has identified new
design implementation issues. To help designers work within
increasingly tighter technical constraints and stricter product
requirements, Reference Flow Release 4.0 pays special attention
to the following new technical issues:
Power
and Performance Optimization:
Take advantage of the power
and speed trade-off of the multiple-Vt libraries and explore
the optimal point that meets the design specification.
Signal
Integrity Closure:
Concurrent timing and signal
integrity (SI) closure encompasses SI prevention, analysis,
and repair. Wire tapering and multiple via insertion address
signal electro-migration issues, while de-coupling cell
insertion targets dynamic IR-drop.
Design
for Manufacturability:
Enables direct manufacturability
in TSMC's nanometer technologies by incorporating the
metal halation rules, redundant via insertion, dummy metal/OD/ploy
insertion and analysis, process variation modeling, and
more.
Login TSMC OnlineSM
Need further information
about TSMC Reference Flow? Please
login to TSMC-OnlineSM
and click on 'Reference Flow' under the Design Portal
category.
Please contact Willy Chen (email address:wlchenn@tsmc.com)
for any question, suggestion, and comment.
專業服務
This
is the industry's first complete design flow that responds specifically
to nanometer design challenges and features dual physical implementation
tracks built around commercial EDA tools primarily from Synopsys,
Inc. and Cadence Design Systems. Reference Flow 4.0 provides
IC design teams with the flexibility to tap into TSMC's recommended
design methodologies independent of tool preferences, while
directly addressing technical challenges related to designing
at 0.13 micron and 90-nanometers. And, for the first time, Reference
Flow 5.0 creates engineering collaboration across the entire
design chain, including chip and package design. 
Power
and Performance Optimization:
