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TSMC Reference Flow 6.0

Foundry Industry's Leading Reference Flow Features Unique Advances in Power Management through Methodology and Library Integration

Power Management
Building upon the company's pioneering Power Closure methodology in Reference Flow 5.0, Reference Flow 6.0 drives power consumption down even further with an advanced methodology and seamlessly integrated low-power libraries targeting TSMC𠏋 advanced low power processes. Reference Flow 6.0 provides new voltage scaling capability supporting multiple voltage islands which gives the designers the full flexibility to take advantage of the full range of dynamic power saving opportunities.

To effectively mitigate leakage power, Reference Flow 6.0 features a unique power gating technology utilizing the multi-threshold CMOS (MTCMOS) design structure to mitigate leakage power. By inserting high Vt footers to shut down the circuits that are not operating, designers can cut the leakage by 90 percent or more, depending on the implementation being used. TSMC is offering the fine grain MTCMOS technology initially, with the coarse grain technology for more leakage reduction coming up later. For both the voltage scaling and power gating techniques, TSMC provides a data retention capability that stores the data during power down and ensures the circuits function normally at wake-up.

Design for Manufacturing (DFM)

At the 65 nanometer technology node, process variance and pattern sensitivity are emerging as major yield influencers. The need to ensure accurate information flow between design and manufacturing is clear. Reference Flow 6.0 follows the tradition of the previous generations by offering key DFM enhancements to improve yield. A new metal fill utility increases metal density and improves metal density uniformity throughout the device. In addition, half-track wire spreading is made available for the first time, to distribute wire more evenly. A couple of earlier DFM guidelines are now part of design rules in 65nm along with the new design rules which were not there in the previous technology nodes. TSMC has proactively worked with EDA partners to embed the OPC-friendly guidelines into commercial tools, and ensured that leading EDA tools support 65nm design rules through rigorous testing with multiple testcases.

Need further information about TSMC Reference Flow? Please log in to TSMC-Online^SM, and click on "Reference Flow" under the Design Portal category.

Please contact Willy Chen (email address: willy_chen@tsmc.com ) should you have questions, suggestions, and comments.

	Reference Flow 6.0 Press Release
	Reference Flow 5.0 Press Release
	Reference Flow Release 5.0