Dr. Cliff Hou's Keynote on "TSMC and its Ecosystem for Innovation"
Invited feature talks by Synopsys, Cadence and Mentor executives
CASE STUDY

TSMC Assists Customers to Improve First-time Silicon Success

2017 Open Innovation Platform® Ecosystem Forum Demonstrated the Achievements of Collaboration with Partners
Jason S.T. Chen
2017/9/13

TSMC held its 2017 Open Innovation Platform® (OIP) Ecosystem Forum on Sept. 13 in Santa Clara, Calif. with over 1,300 attendees. The annual event demonstrates how TSMC and our ecosystem partners jointly develop design solutions on top of TSMC's advanced technologies through OIP collaboration.

Dr. Cliff Hou, TSMC Vice President of Design and Technology Platform delivered his keynote on TSMC's design enablement platforms, together with each platform's respective solutions jointly developed and delivered with OIP partners. Feature talks by three executives of TSMC's EDA/IP partners followed, highlighting their long-term collaboration with TSMC that helps customers innovate and capture market opportunities.

TSMC's Technology Development and Solutions Address Market Demands with Four Application Specific Design Platforms

During his keynote, Cliff highlighted that to help our customer products' time-to-market, TSMC has expanded design ecosystem solutions to address market demands with four application specific design platforms consisting of Mobile, High Performance Computing (HPC), Internet of Things (IoT) and Automotive. In addition, TSMC continues to enhance 3DIC solutions to integrate High Bandwidth Memory (HBM) on Integrated Fan-Out (InFO) design flow to meet customer's system integration and high memory bandwidth requirements. Furthermore, machine learning is being leveraged to enhance customer design Power, Performance and Area (PPA) and productivity.

For Mobile Design Enablement Platform, 7nm EDA & IP solutions are ready and have been used in customer's production. 7nm+ is enhanced in PPA from 7nm with migration utility and layout service available to support customer's design porting.

For HPC Design Enablement Platform, TSMC further enhanced 7nm and 7nm+_ in process and design solutions to support HPC speed and memory bandwidth requirements. TSMC has demonstrated a 4Ghz ARM core and provided the first Cache Coherence Interconnect for Accelerator (CCIX) silicon demonstration vehicle in 7nm process technology with Xilinx, Arm and Cadence.

For IoT Design Enablement Platform, 22ULP_ULL is enhanced significantly from 28nm analog and RF capabilities to support low power leakage requirements in 5G, millimeter Wave and connectivity applications.

For Automotive Design Enablement Platform, TSMC further optimizes process, IP, and EDA offerings to meet automotive quality, functional safety, and reliability requirements. We have built our first automotive design enablement platform on 16FFC and progressing toward 7nm now. For existing process nodes such as 55nm, 40nm, and 28nm, TSMC will provide an automotive service package, and optimized processes to meet customer's requirements.

Apply Machine Learning Innovation to Enhance Customer Design and Productivity

TSMC pioneered machine learning in IC Design to make early tradeoff and design decisions based on the high quality prediction made possible by machine learning technologies. TSMC assists customers to boost performance, reduce area, optimize productivity, and obtain competitive advantages when they design their new products in TSMC's advanced 7nm technology.

Through machine learning, TSMC design enablement platforms produce optimized design constraints and EDA tool scripts, while supporting customers to best utilize the commercial EDA tools from our OIP ecosystem partners.

This collaboration model enables TSMC and our OIP ecosystem partners to focus on our respective strengths, while creating synergy to team up and bring machine learning innovation to the whole design community.

Ecosystem Partners and Customers Shared Best Practices with TSMC's Advanced Technologies

Three parallel tracks of EDA, IP and design services were arranged with a total of 33 technical paper sessions for OIP partners and customers to jointly present their capabilities and solutions detailing how they design with TSMC's process technology to meet product requirements at different design stages for different types of design applications.

The Ecosystem Pavilion also featured booth exhibitions from 60 ecosystem partners showcasing their products and services.

Readiness of Ecosystem Solutions for Customer's Adoption to Harvest the Benefits from Process Technologies

EDA tool certification is an essential foundation for IP and customer designs to ensure the features meet TSMC process technology requirements. The reference flows are built on top of certified tools to provide additional design flow methodology innovations that can help boost productivity. For instance, there are now a via-pillar aware solution flow for HPC design, as well as a reliability and power integrity flow for 3DIC design. There are corresponding technology files and Process Development Kits (PDK) available for customers to download and design together with certified EDA tools and reference flows.

IP is the basic building block of integrated circuit designs. Different IP types of foundation IP, analog IP, embedded memory IP, interface IP and soft IP, are available to support different types of customer design applications.

For TSMC's latest advanced technologies of 7nm, 12nm and 3DIC design enablement platform, EDA tools, features, and IPs solutions are readily available for customers to adopt to meet their product requirements at various design stages. Both accumulated EDA deliverables and IP portfolio of TSMC's technologies have helped lead to customer's successful tape-outs.

Accumulated EDA Deliverables from 0.13μm ~ 7nm that have been successfully supporting customer tape-outs

Accumulated 16,000 IP titles portfolio from 0.35μm ~ 7nm with major IP types to meet customer design needs