TSMC recently announced that its in-house developed 90nm standard cell and I/O libraries are now available for IC design starts. The libraries were developed by the Design Service Division in concert with the Nexsys 90nm process technologies and reflect design rules and SPICE models defined while the process was still in development. The new TSMC 90nm libraries were developed using various benchmark circuits to extensively exercise the process " front-end and back-end flow " (synthesis, P&R, and full back-end flow). Design for manufacturability (DFM) features have been added without compromising either performance or density. The libraries have recently been manufactured into silicon and tested for functionality and performance.

The Nexsys 90nm libraries are just the latest in a whole family of TSMC internally developed libraries that have been designed so that early development partners could help ramp "next generation" processes. During process development, design rule and SPICE model changes occur. Some of these changes are critical for better manufacturing margin and are implemented as soon as possible to ensure that all libraries are current to the most recent design rule and SPICE model versions.

Collaborations with leading EDA tool suppliers further facilitate library development. More advanced features, such as Signal Integrity (SI) check and correction and Electromigration (EM) prevention, cannot be accomplished without full collaboration from these parties. The Nexsys 90nm standard cell libraries feature multiple threshold options and an optimized standard cell architecture developed concurrently and synergistically between library and process teams under a single R&D organization. The libraries integrate high-speed and low-leakage functionality using mixed and matched multiple threshold voltage (Vt) library cells. The standard cell libraries are developed for the 90nm general purpose process in nominal threshold voltage, low threshold voltage and high threshold voltage, as well as low power and high speed derivatives. The products are characterized by TSMC's latest electrical models, fully complied with TSMC's 90nm design rules and comprehensive design-for-manufacturability features. The libraries contain an extensive set of logical models and physical design views used by industry-leading EDA tools. The Nexsys 90nm standard cell libraries provide a wide variety of cell types with multiple drive strengths. The new cell architecture enhances density and speed, as well as reliability. Library cells are tuned for optimal logic synthesis and routability results. High drive strength cells are constructed to support wide wire-width signal routing for EM and critical path timing. Diodes are built-in into key buffers for process antenna charging prevention. Decoupling capacitors are available for high-speed switching power and ground noise reduction. The 90nm libraries are integrated with TSMC Reference Flows and major EDA vendors' design flows. Vendors' logic synthesis, as well as placement and routing suites, have verified TSMC library performance and robustness. Logic models for the standard configuration of TSMC Nexsys 90nm standard cell libraries are available immediately for general purpose processes, with three types of threshold voltage, and the low power process. The library for the high-speed process is expected to be available in the fourth quarter of 2003. TSMC also offers, in pre-silicon release status, three sets of 90nm standard I/O libraries. The standard I/O libraries cover three commonly used interface voltages: 1.8V, 2.5V, and 3.3V. Each library is for staggered bonding application and does not support input high-voltage tolerance application. Input high-voltage tolerant version of each library will be offered in Q1, 2003. The test chip for 1.0V/2.5V version is currently under evaluation and the library functionality has been proven. Once ESD solution is verified, the library will be available for production design. The 1.0V/3.3V version test chip is also in evaluation. Standard I/O libraries for Nexsys 90nm low power and high speed technologies are also in the planning stage and could reach pre-silicon release status in the fourth quarter of this year. Analog I/O libraries for all three technologies will be offered in pre-silicon release in the fourth quarter of the year. TSMC 90nm libraries are available on TSMC-Online and through several recently announced library distributors. The libraries will be released in the very near future. Please contact our Account Mana-gers or FieldApplication Engineersfor the details.

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