In Depth
  TSMC's Nexsys 90nm process is now in full production at our state-of-the-art 12-inch fab, located Hsinchu, Taiwan. This is the world's first 300mm, low-k, 90nm process to reach full production, which we accomplished after one year's ramp. There are more than 30 products (single product mask sets) running in Fab12, in either the pilot or volume production stages, with 12-inch wafer output of more than 3,000 per month. Among these products, communication and consumer chips, such as cellular phones and DVD recorders, are the demand forerunners for 90nm production. In addition to volume, product yields demonstrated in Fab12, are currently ahead by at least one quarter of our defect density goals. Cost savings from using 12-inch wafers combined with the low defect densities achieved with TSMC's Nexsys 90nm means that there are significant benefits for migrating from 0.13-micron or above.  

  Commenting on this migration, TSMC VP of Corporate Marketing, Dr. Genda Hu said, "The transition to the 90nm manufacturing node is much smoother than the transition to the 0.13-micron node a couple of years before it. We can further leverage these gains through our past experiences with 0.13-micron. Lessons learned in the past with the low-k 0.13-micron generation, have already resulted in the quick 90nm ramp."

  
  TSMC anticipates that initial 90nm volume will be driven by the communications market. More than 50 percent of TSMC's 90nm tape-outs are communication applications.  

  Cell phone baseband chips, targeted to the low power process, will be the first devices to enter full production, followed shortly by several wire line products that use the general purpose processes. Other 90nm process drivers include multiple programmable logic devices.  

  "Altera's ramp of the 90nm process is going extremely well and we are on track to have all six members of our Stratix II FPGA family verified for production by the end of the year," said Francois Gregoire, vice president of Technology at Altera Corporation. "This smooth ramp is the result of three years of intense partnership, during which the design and process teams have worked closely together to solve all critical issues; including 'design for manufacturability,' low-k, power management, and performance optimization. The end result of this partnership is that Stratix II is unrivaled in terms of density and performance, and yields are better than any previous technology at the same stage."  

 
 

  Nexsys 90nm capacity will only be available in 12-inch fabs, starting in 2004 with Fab12A, followed by Fab12B/C in the second quarter of 2005. Fab14, located in Tainan, Taiwan, will have capacity in the fourth quarter of 2005. This figure is expected to triple in the second half of 2005.  

  TSMC Nexsys 90nm technology includes a CyberShuttleSM service starting March 2005. CyberShuttle provides inexpensive and speedy solutions for verification of sophisticated multi-million transistor designs. TSMC is currently offering an incentive program for our 90nm shuttle. Contact your account manager for more information, or refer to TSMC-Online for updated shuttle service details.

The Nexsys 90nm family includes general purpose (CLN90G), low power (CLN90LP) and high performance (CLN90GT) process options. All of these options provide Deep N-well (DNW), top-2 thick metal layers, electrical fuse, ultra-high-density SRAM and Aluminum or Copper RDL (redistribution layer) options. Derivative technologies include mixed-signal and radio-frequency processes, and 1T-MiM (CTN90GT). Three micron copper inductor and MiM/MoM cap are standard mixed-signal and radio-freguency processes.

For additional information, contact your account manager or visit www.tsmc.com.