TSMC has announced the availability of embedded 1TRAM memory in its 0.13-micron logic process, providing a superior, reliable and cost-effective alternative to conventional embedded DRAM. With an optimized memory cell, the embedded 1TRAM requires only about 2.0mm2 to store one millions bits and is compatible with logic design rules.

"TSMC has been in volume production with embedded 1TRAM-based products since the 0.25-micron generation, which means we have a history of manufac-turing these products with high yield. To meet the strong demand for embedded memories in wide-variety of applications, across all market segments, TSMC is rolling out 1TRAM in the leading-edge 0.13-micron CMOS technology." said Dr. Sam Chu, Director of Embedded Memory Marketing at TSMC.

Embedded 1TRAM designs are supported by TSMC's 0.13-micron triple-oxide family that includes General Purpose (G), Low-Power (LP), and Low-Voltage (LV) options. Together with design partner MoSys, TSMC has recently completed process and product qualifications in 0.13-micron G and LP processes. The Low-Voltage process will be ready in 4Q 2003.

Multiple Generations in Full Production

TSMC has been providing 0.25, 0.22, and 0.18-micron Emb1TRAM processes since 2000, and extended it to the 0.13-micron node in 2002. All four Emb1TRAM generations have undergone strict process and product qualification, governed by the well-established qualification program -
TSMC9000. Emb1TRAM's robust planar memory cell ensures low failure rate even under stress. No burn-in is needed for most applications and backend testing is greatly simplified.

Multi-banking and ECC Enhance Emb1TRAM Performance

Emb1TRAM is not what 1T-cell technology used to be back in the '70s. The difference is the adoption of Emb1TRAM's sub-10-femptofarad cell capacitor (Figure 1a). This cell capacitor features multi-bank partitioning, a design innovation with finer array partitioning and shorter bit lines (Figure 1b). Shorter bit lines reduce interconnect RC delays. As a result, the memory cell is smaller, the active power dissipation lower, and the operating speed faster.

Error Correcting Circuits (ECC) are standard in all 0.13-micron Emb1TRAM macros. Integrating ECC improves data retention time by more than ten-fold (Figure 2). It also reduces the soft error rate (SER),
as the table shows.

Compact and On-Chip--Ideal for High-Bandwidth, Miniature, and More

Embedded high-density memory is crucial to high-bandwidth applications such as networking, electronic games, and high-performance graphics. By using a wide on-chip bus with Emb1TRAM, the system bandwidth is dramatically expanded without using costly packaging. The compact 1TRAM memory macro is also ideal for today's miniature consumer applications. Furthermore, Emb1TRAM can be seamlessly integrated with other technologies, such as CMOS Image Sensor, or embedded flash memory, in various SoC designs.

TSMC has been shipping Emb1TRAM wafers in volume for more than two years. Product proven and scaled across 0.25, 0.22, 0.18, and 0.13-micron technologies, TSMC Emb1TRAM opens new horizons that offer unlimited design-win opportunities.