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TSMC Reference Flow 4.0 is the first reference flow to include dual physical implementation tracks built around commercial EDA tools from both Synopsys and Cadence. This dynamic feature provides design flexibility and is expected to further lower the barriers to acceptance. TSMC became the first foundry to include reference flows as a standard design offering when it announced the availability of Reference Flow 1.0 in April, 2001 and since then, has added reference flow releases that cover a spectrum of design implementation needs for different technology nodes and different design characteristics. |
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Take Advantage of Nanometer Technologies Reference Flow 4.0 pays special attention to some new technical issues that appear challenging in the nanometer frontier. These issues include: Signal Integrity -- Conducts concurrent timing and signal integrity (SI) closure, including cross-talk prevention, analysis, and repair. Wire tapering and multiple via insertion address signal electromigration issue. De-coupling cell insertion addresses dynamic IR-drop. Power and Speed Optimization -- Takes advantage of the power and speed trade-off available through multiple-Vt libraries and explores the optimal point that meets the design specification. Design For Manufacturability -- Enables direct manufacturability in TSMC's namometer technologies by incorporating metal halation rules, redundant via insertion, dummy metal/OD/poly insertion and analysis, and process variation modeling.
Along with the evolution of
process technologies, TSMC has anticipated the design challenges for each
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