The 41 International Reliability Physics Symposium (IRPS), held April, 4 in Dallas Texas, opened with a keynote address by Dr. Shang-yi Chiang, TSMC's Senior Vice President of Research & Development. In his address, "Technology & Reliability Challenges in the Foundry Business", Dr. Chiang outlined the foundry technology model and the associated reliability challenges in foundry era.

"Given the prevalence of SoC design and advanced packaging requirements, foundries must take a serious look at how to bridge the gap between design, manufacturing and assembly. We must integrate the whole supply chain to meet immediate and future market requirements, "Dr. Chiang pointed out. "And while foundries must provide diversified technologies and reliability assurance for various applications, we must also establish collaborated efforts with each of our design and assembly partners," he added.

While Dr. Chiang may have been the most visible TSMC participant, other members of the company's technical staff played active roles in this year's event. Dr. Anthony Oats, Technical Director. Quality & Reliability; Dr. Kenneth Wu, Director, Reliability Division; Dr. David Su, Deputy Director, Failure Analysis Division; and Dr. Yeng Peng, Senior Director, Quality & Reliability were all involved in the management and technical commitees of this year's conference.

In addition, company authors presented the following papers:

"Stress-induced Voiding and Its Geometry Dependency Characterization" by Kevin Y.Y. Doong,
　Robin C.J. Wang, S.C. Lin, L.J. Hung, S.Y. Lee, C.C. Chiu, David Su, Kenneth Wu,
　K.L. Young and Yeng Peng.

"An Improved Interface Characterization Technique for a Full-range Profiling of Oxide
　Damage in Ultra-thin Gate Oxide CMOS Device" by S.J. Chen, T.C. Lin, D.K. Lo, J.J. Yang,
　S.S. Chung, T.K. Kao, R.Y. Shiue,C.J. Wang, and Yeng Peng.

"The Failure Mechanism of the High Voltage Tolerance IO Buffer under ESD" by Jian-Hsing
　Lee, J.R Shih, Y.H. Wu and T.C. Ong.

"Investigation of Wafer Level Burn-in to SoC Memory: 1TRAM" by Y. L. Pan, S.H. Chen,
　C.H. Lu and J.J. Wang.

"The Study of Compressive and Tensile Stress on MOSFET's I-V, C-V Characteristics and
　It's Impacts on Hot Carrier Injection and Negative Bias Temperature Instability" by
　J.R. Shih, J.J. Wang, Kenneth Wu, Yeng Peng and J.T. Yue.

"Real Case Studies of Failure Mechanisms for Cu Trench Eletromigration" J.B. Lai, J.L. Tang,
　 H.W. Yang, R.L. Hwang, David Su, Harry Chuang and Y.S. Huang.

The 2002 TSMC Total Quality Excellence (TQE) Conference was held in Hsin-Chu, Taiwan, under the theme of "Learning, Innovation, Value". This annual event encompassed 66 TSMC departments and acted as the platform for 1,085 TQE case studies from all corners of the company. Twenty-one teams qualified for the final TQE competition.

First started in 1995, the conference's program recognizes employees' quality improvement initiatives and acts as a forum to help spread the best quality practices across TSMC. At the conference, employees present continuous improvement results and share experiences across departments. The number of teams participating in the event has increased from seven in 1995 to 1,085 teams who participated in the most recent event. In total, Continuous Improvement Team (CIT) initiatives saved TSMC nearly NT$32 million last year.