TSMC : Foundry Watch

Nexsy 90-nm Process Enters Production

TSMC Nexsys^SM 90-nanometer Technology for SoC process is ramping to full production status at the company's state-of-the-art 12-inch fab, Fab12. Currently, there are 20 products running on 90-nanometer. Most are "first-cut" functional and demonstrate good performances.

"We are quite satisfied with the 90-nm process performance and yield to date," said John Wei, Senior Director of Advanced Platform Marketing.

Three reasons behind the smooth ramp: There are no new dielectric materials, nor interconnect materials, nor wafer sizes at this node. TSMC is the only foundry to offer its standard 90-nm process with low-k dielectrics on 12-inch wafers.

The Nexsys 90-nm family includes general purpose (G), low power (LP) and high performance (GT) platforms. All of these platforms support features such as deep N-well (DNW), top-two thick metal layers, electrical fuse, ultra-high-density SRAM and aluminum or copper redistribution layers. The operating voltage is 1 volt to 1.2 volts; the I/O voltages range from 1.8 volts to 3.3 volts. SRAM memory densities range from 1.65-micron² to 0.99-micron².

Derivative technologies include mixed-signal, radio-frequency, and 1T-MiM. A 3-micron copper inductor and MiM/MoM cap are standard in RF. The 1T-MiM, which is also ideal for ultra-high density memory applications will also be offered on the high performance platform first and other platforms later.

Compared to TSMC's 0.13-micron process, the 90-nm process provides twice the gate density, a 35 percent speed improvement, a 60 percent improvement in active power savings, and a 20 percent interconnect RC improvement. All comparisons are based on a general-purpose 101 stage ring oscillator.

TSMC's Nexsys 90-nm process is a full system-on-chip platform providing both CMOS logic and mixed-signal options with embedded high-density memories, including 1TRAM, 6TRAM, 8TRAM and electrical fuse technology. In addition, the new process features multiple transistor types for improved power/speed/leakage tradeoffs.

Communications Market Drives Adoption

TSMC anticipates that initial 90-nanometer volume will be driven by the communications market. More than 50 percent of TSMC's 90-nm tape-outs are communica-tion applications.

Cell phone baseband chips targeted to the low power process will be the first devices to enter full production, followed shortly by several wire line products that use the general purpose process. Other 90-nm process drivers include multiple programmable logic devices.

Initial Fab 12 Production
All of the TSMC 90-nm products will be built exclusively on 12-inch wafers. First production will come from Fab 12, with production originating from Fab 14 in early 2005. By the first half of next year, TSMC anticipates that total 90-nm shipment will exceed 120,000 8"-equivalent wafers and will more than double that number in the second half of the year.

Nexsys 90-nm prototyping services are available on TSMC 's CyberShuttle^SMservice every quarter. Refer to TSMC-Online^SM for the most up-to-date shuttle information.