TSMC : Foundry Watch

In Depth

TSMC made a resounding statement about its foundry industry design metho-dology leadership with the introduction of Reference Flow 5.0, the industry's first design flow to address the critical power closure design challenge.

The insatiable demand for increased functionality and longer battery in portable appliances requires the most advanced process technologies. But the challenges of nanometer design are almost as daunting as the specs they support. While advanced process technologies provide the requisite hundreds of millions of transistors, they also challenge the validity of previously held power assumptions; namely those dealing with power as uniform and fixed on-chip supply voltages.

To meet power target and to ensure promised device performance, designers not only have to reduce power consumption, but also must mitigate power integrity issues.

Minimizing Power Consumption Becomes Paramount
Greater appliance functionality requires device designs that integrate greater numbers of transistors on a single chip. As result, today's designs consume huge amounts of dynamic power. As supply voltage decreases and as thermal effects increase, power leakage in transistors also increases. To effectively reduce the overall power consumption, designers must optimize both dynamic power and leakage power.

Reference Flow 5.0 resolves this challenge by introducing both power shutdown and voltage scaling methodologies to reduce power consumption when a device is in sleep mode and standby mode. Through Reference Flow 5.0 designers can insert isolation

cells into their devices to prevent the leakage caused by unknown state outputs from shutdown areas. In addition, level shifters are inserted to link different power domains. Specifically, for leakage power reduction, we are introducing a new methodology - substrate bias.

Power Integrity Changes Design Equations
As supply voltages in advanced technologies decreases, designers find themselves working with lower voltage noise margins. This emerging power integrity issue changes the entire design equation, making obsolete previous assumptions about uniform and fixed supply voltage . As a result, it has become imperative to address power integrity issues or risk the very real probability of inadequate device performance.

Power integrity is dynamic in nature. Consequently, the well-accepted static IR-drop solution (based on average current, average toggling rates, pure resistive power network, and over design) does not completely solve the problem. For example, static analysis overlooks voltage collapse, which is caused by simultaneous switching. Furthermore, it is not realistic to over-design for these sudden voltage supply noises.

Reference Flow 5.0 enables designers to perform comprehensive IR-drop analysis including core logic, I/O and package analysis. In addition, its dynamic IR-drop analysis capability considers simultaneous switching effects. Finally, Reference Flow 5.0 helps designers insert decoupling cells to mitigate the transient IR-drop effect.

Integrated Chip and Package Design
Packaging is no longer a "plug and play" component in the design chain. Package-related physical and electrical effects are now important considerations for high-integration, high-frequency designs.

For the first time, Reference Flow 5.0 promotes collaboration all along the design chain and bridges the previously disconnected worlds of chip and package design. Designers can now perform integrated chip and package routing analysis and LVS. These new capabilities boost overall productivity by shortening cycle time and eliminating error-prone interaction between independent chip and package designs. Integrated chip and package IR-drop analysis and static timing analysis further ensures the design's electrical performance.