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Electron Beam Backscatter Diffraction |
| The study of electromigration
(EM) and stress migration (SM) is a prerequisite for understanding the reliability
of integrated circuits. Microstructures, such as grain size, grain orientation,
and crystallographic texture, are known to have a significant correlation
with reliability performance. Traditional approaches, such as X-ray diffraction (XRD) and transmission electron microscopy (TEM), have limitations when used to analyze the microstructure of copper interconnects. XRD lacks spatial resolution and TEM requires unacceptably long times to acquire a statistically significant amount of data. Electron Beam Backscatter Diffraction (EBSD) (also known as Orientation Imaging Microscopy (OIM)) provides valuable local microstructural information without the limitations of XRD or TEM technologies. The failure analysis laboratory at TSMC has a TexSEM OIM system installed on a LEO 1530 secondary electron microscope (SEM). This tool was used successfully for studying aluminum-based metallization. However, when this method is applied to copper low-k dielectric samples, factors such as charging, drifting and instability of the low-k material can seriously compromise the quality of the EBSD data. Focused ion beam-based (FIB) sample preparation techniques, for both top view and cross-sectional samples, have been developed at TSMC to minimize these effects and enable acquisition of quality EBSD data. |
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Future Gate Dielectric Reliability Challenges |
| Gate dielectric
thickness has rapidly decreased to the range of 15 - 17Å over the
last several technology generations, and this rapid scaling has caused two
significant concerns. First, there is a significant increase in the gate
dielectric leakage current, which reaches levels of the order of 100Å
/cm2 for 12Å thick SiO2.
Second, there is the potential for decreased gate dielectric reliability.
Below about 30Å , the gate oxide failure signature changes from a
hard electrical breakdown, where the gate dielectric abruptly shorts the
silicon channel to the gate, to a soft electrical breakdown, where the gate
current gradually increases with time. Gate dielectric leakage reduction remains the major challenge for future gate dielectric development, particularly for low power and mobile applications where battery life considerations limit allowable circuit leakage levels. TSMC is actively developing alternative gate dielectric materials with higher dielectric permittivity (high-k). The advantage of these materials is substantially decreased (~103) direct tunneling leakage current for the same electrical thickness as SiO2, as a result of their increased physical thickness. The first step on this road has already been taken with nitrogen-doped SiO2 (SiOxNy), which is already in use for TSMC's most advanced manufacturing technologies. In terms of SiO2 replacement, interest is now centered on HfO2 - based dielectrics. Reliability characteristics that closely match, or exceed, those of SiO2 will be one of the primary goals of future high - k development work. High - k materials exhibit much higher levels of fixed charge than SiO2, leading to new reliability phenomena such as NMOS Vt instability. Additionally, the band structure of high-k gate stacks is asymmetric due to presence of SiO2 interfacial layers at the Si surface. This asymmetry results in voltage polarity dependent degradation phenomena. Attainment of acceptable reliability, and the development of methodologies to characterize and qualify these materials for manufacture is a challenging and exciting goal for future development work at TSMC. |
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| The second challenge
- that of reliability characterization - has been to understand the impact
of the soft electrical breakdown phenomenon on transistor and circuit characteristics.
Extensive studies at TSMC and elsewhere have shown that following soft-breakdown
the transistor remains operational, but at the expense of modest increases
in gate current. Despite some initial concerns that soft-breakdown would
present a limitation to gate oxide scaling, recent improvements in our understanding
of this effect now shows there is no fundamental reliability limitation
to scaling of SiO2 gate dielectrics even to 11 - 12Å
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