"Get it right the first time" is more than the design mantra de-jour.
More and more, it's a necessity for economic survival.

As costs rise and product cycles shrink, designers are under increased pressure to "get it right" the first time. TSMC assists in accomplishing this nearly-impossible task by collaborating early in and throughout the design cycle. By sharing design-for-manufacturing techniques (DFM), our knowledge of silicon effects, processing details and manufacturing options, we have often helped our customers increased yields and reduce overall chip costs.

As process nodes shrink, wafer processing costs, mask creation, EDA tooling and engineering time increase:

	Process technology complexity rises with each new process generation as ever more exotic materials and stringent tolerances are required.
	Each new process generation requires larger, more detailed masks to handle denser features and higher gate counts.
	Design techniques require careful analysis and state-of-the-art tools to cope withincreasing noise generation sources and increasing noise sensitivity modes.

Then too, there are fab-level manufacturing considerations that complicate the situation. Most notable is the need to extend the life of optical equipment through optical proximity correction (OPC) and phase-shift mask (PSM) sets for deep-sub-micron processes. This results in photomasks that are very complex for 180nm processes and below, particularly for mask layers such as polysilicon that define minimum-feature geometries.

Taken together, these considerations have driven SoC NRE cost to several million dollars for very complex chips. Increasing NRE moves the chip-volume 'breakeven point'- the volume at which NRE expenses are recouped - to ever-higher levels. This puts pressure on fabless companies and integrated device manufacturers (IDMs) alike to reduce development costs and eliminate design iterations. Shorter times-to-market, due to market competition, also push the need for first-time chip success. For many products, first-time success literally spells the difference between reaching product ROI targets and red ink.

Working Towards First-Time Silicon Success

The need for properly working first-time silicon is easily explained. Making it happen is the hard part. There are many factors that contribute to first-time silicon success, including design tools, design methodologies, cell libraries, and silicon IP. Each one requires examination to determine the fastest path to first-time success designs, with minimum design time and expense.

Design Tools

A good EDA tool set is critical. From a top-level view, these tools cover three chip development areas: front-end design, backend design, and design verification.

Front-end tools take the design from conceptualization through completion of the logical portion of the chip, comprising such tasks as system-level design and analysis, register-transfer-level (RTL) design and analysis, and logic synthesis and optimization to a logic-gate-level representation of the chip. Front-end design may also include some level of floor planning to aid in design verification prior to the chip's physical implementation.

Backend design, describing how structures will be physically implemented on the chip, centers on the placement and routing of the chip's silicon cores and library cells. During physical design, place-and-route (P&R) tools have more accurate knowledge than front-end tools of interconnect parasitics that affect the chip's timing. This knowledge allows a P&R tool to perform design optimization as well as define the physical layout of the chip. P&R tools help designers meet constraints such as speed, power dissipation, and silicon area. Backend designers must use models of devices and wires that accurately reflect what the silicon will show. This requires strong ties to whoever is doing the processing of that particular chip. Collaboration between EDA vendors and a silicon foundry is important in order to achieve maximum backend tool benefit.

The most time-consuming chip design operations involve design verification; i.e., making sure the chip meets functional, timing, power, and other specifications. Verification can take up to 70% of total design time, since it must be performed at all design levels-system, RTL, gate, and physical, the latter with extracted device and interconnect parasitic values.

Design Methodology

Even with the best available tools, a proper design methodology minimizes design time and enhances the chance of successful first-time silicon. The design community in recent years has focused on timing closure-meeting chip timing performance after design extraction from the physical database with the specified timing performance detailed during front-end design. While timing closure is very important, there are other design parameters that are also critical for most very deep sub-micron designs, specifically power, signal integrity (SI), and reliability. The final goal is design closure, whereby a chip meets all of its design onstraints.

A good design methodology utilizes analysis and verification criteria throughout the entire design flow, starting from initial estimates at the system level and getting increasingly more accurate numbers as the design progresses from the front-end stage to the physical design operations. Foundry design guidelines are useful in helping meet chip specification goals. At 90nm, static power due to device leakage (standby power) is comparable to dynamic power on a chip. TSMC offers a reference design flow guideline to minimize leakage. The guideline works by using high-performance (low VT) transistors for the entire chip during the initial front-end design flow; specifically logic synthesis and optimization. This corresponds to using the fastest cell library available for the target process, letting the designer optimize the chip for timing and area. After backend placement and routing, followed by parasitic extraction and timing analysis, the designer can identify timing paths with positive timing slack those paths that are faster than required for meeting the chip's timing specification.

Paths with positive timing slack indicate places where the designer can substitute high VT transistors for low VT devices. High VT transistors have slower switching speed, but also exhibit less leakage current and lower static power dissipation. Substituting high VT for low VT transistors does not affect the chip's layout. Through repeated substitution and static-timing analysis, the designer can help meet timing specifications, but with a significant power reduction. For example, a reduction of standby power by a factor of five or more and a reduction of dynamic power by a factor of two or more is not unusual.

TSMC also has design guidelines for meeting SI and reliability criteria, addressing areas uch as:

Crosstalk prevention, analysis, and repair
Electromigration for both power and signal lines
De-coupling capacitors

Design Libraries

Another key to first-time silicon success is accurate modeling of the cells and cores. Cell libraries must have good models available at several design levels-RTL, gate, and physical. The designer should have a rich choice of library functions and cell types-low power, high speed, and high density. In line with power minimization, TSMC's partners offer library cells with multiple VT values to allow designers to achieve concurrent timing and power optimization. Furthermore, these libraries are validated by TSMC in the leading design flows from Synopsys, Cadence, and Magma.

TSMC has its own validation standard for the most popular cell libraries and SRAMs. Based on the well-known ISO9000 standard, TSMC9000 is the most rigorous validation standard in the silicon foundry industry. TSMC9000 describes what is in a library package in great detail, including EDA views, process corners, test-chip standards, testing protocols, production criteria, and other important design and validation information. The standard's multiple levels of qualification help raise customer confidence in reaching silicon success.

Silicon IP

TSMC also applies this "show me the silicon" philosophy to silicon IP. Towards this end, TSMC requests a validation status report for all third party and internally-developed IP cores. Silicon-validated IP include processor cores, DSP engines, specialty I/Os, and mixed-signal functions from several leading vendors.

DFM Issues

Along with exhaustive sets of design rules, TSMC also provides a design reference flow that addresses several DFM issues:

Process-variation modeling
Dummy OD, polysilicon, and metal insertion
Metal over via/contact enclosure
Redundant via insertion

Copper is softer than aluminum relative to the surrounding dielectric. This means that copper interconnect wafers exhibit uneven wire thickness across a chip, with the thickness in any region a function of wire width, wire spacing, and local metal density in that region. This translates electrically to variable interconnect sheet resistance over the chip and, hence, variable parasitic delay even for wires of equal length. This phe-nomenon can be significant for 130nm and below chips, particularly for faster inter-connect paths. In Figure 2, a line with nominal 3ns delay has a difference in path delay between simulations with and without intra-chip metal variation modeling of around 125 ps, about 4.2%. However, for a path with a nominal 1ns delay, the difference can be as much as 80 ps or 8%, which is significant. To reduce timing simulation 'surprises', intra-chip metal variation modeling is an important factor to include in chip design flows.

TSMC's recommendation is to use dummy metal insertion to increase copper uniformity across a chip to reduce intra-chip metal variation. A key consideration in dummy geometry insertion is to minimally increase OPC for the chip, since OPC operations are very compute- and time-intensive, and to minimally increase the parasitic capacitance load of signal lines. TSMC and its EDA partners have recommended design flows to perform this operation with the goal of minimizing OPC computational consequences and parasitic electrical consequences.

For chip designs at 130nm and below, TSMC specifies a set of minimum design rules and, additionally, suggests a set of stricter design guidelines to enhance yield. For example, in addition to double vias on wide metal lines, TSMC recommends a redundant via insertion methodology to enhance chip yield wherever there is room to add larger via structures. The methodology comprises four stages-fat double via, normal double via, fat single via, and normal single via-as shown in Figure 3.

Figure 4 shows TSMC's reference flow to correlate design flow with real silicon. The flow addresses many of the previously described issues along with several others. Key flow features are:

	Power and performance optimization using multi-threshold power tuning
	Concurrent timing and signal-integrity closure
	Nanometer DFM challenges including layer density, layer resistance, and via placement

TSMC invests heavily in design know-how. In addition to building internal design competence, TSMC recruits design partners in the EDA, library, IP, design service sectors. The product of this investment is a set of design building blocks, flows, and services that help throughout a chip's design.

Designers can use these products to help achieve first-time silicon success.