The 45nm Process Family

The 45nm logic family includes the Low Power (LP), General Purpose Superb (GS) and low-power triple gate oxide (LGP) process options. All three processes offer multiple threshold voltage (Vt) core devices and 1.8V, 2.5V, 3.3V I/O options to meet different product requirements.

The 45nm LP process provides double gate density of 65nm with significantly lower power and manufacturing costs per die making it ideal for small footprint designs like those used in cell phones, portable media players, PDAs and other handheld devices.

The 45nm GS processes provide more than twice the density, same leakage, and more than 40 percent speed enhancement to the counterpart TSMC 65nm process, and are targeted for PC, networking and wired communication applications.

45nm Design Ecosystem

In-house design, backend and design ecosystem services round out TSMC¡¦s 45nm platform to accelerate rapid tapeout and adoption.

The design ecosystem includes:
	Prototyping: TSMC's prototyping programs streamline the transition from first silicon to production, including the QuickStart(SM) IP program, the Prototype Diagnostics Alliance and CyberShuttle(SM). CyberShuttle allows multiple customers to share the costs of a single mask set and prototype wafers on a pilot run.
	Extensive libraries and IP: TSMC's 45nm design ecosystem includes the industry's most advanced technology libraries, including standard cell, standard I/O, single-port SRAM, dual-port SRAM and more. The Library Alliance Program supports TSMC's extensive portfolio of silicon-proven third-party IP.
	Process design kit (PDK) quality assurance: TSMC 45nm PDKs cover the entire design flow from schematic entry, simulation, layout, and layout check to post-simulation. The 6-stage automatic PDK quality assurance flow with over 133 procedures ensures consistent quality control and faster development lead time. Adoption is simplified with smart installation and tutorial, and design accuracy is improved with support for well proximity effect (WPE) modeling, Monte Carlo simulation, and estimated parasitic RC device information for pre-simulation.
	Design for Manufacturability (DFM): TSMC's 45nm (DFM) initiative goes beyond traditionally supplied design rules and SPICE models, providing additional manufacturing variance data that is essential for achieving high yields at the nanometer level. A model-based approach and a rule-based approach are available for designer implementation, with a DFM Data Kit (DDK) for third-party EDA tools and a TSMC DFM toolkit with advisories and utilities.

Successful CyberShuttle runs for 45nm chip and IP prototypes have proven the platform and are scheduled on an ongoing basis. Production for 45nm is expected to begin Fall 2007.