Advanced Embedded DRAM Technology
The embedded DRAM celll with Metal-Insulator-Metal capacitor features
a capacitor-under-bitline (CUB) that reduces both process complexity
and the number of production masks. It provides additional cell area
improvements and can integrate up to 256Mb of on-chip memory.
For more information, contact your account manager.
Error Correction Code (ECC) Design Ensures High Yield and
Excellent Reliability
Both 1T-Q and embedded DRAM feature ECC to improve high yield success.
Neither requires memory burn-in, which reduces production costs.
The Soft Error Rate (SER) is more than 10 times better than 6T-SRAM
technology’s.
Robust TSMC and Third Party IP
TSMC partners with the industry’s best 1T IP providers. Starting
from 90nm, TSMC provides embedded DRAM IP option. Different memory
densities with 1Mb granularity and configurable bus widths ranging
from 32-bit to 512-bit are available. Low power application options
include sleep mode, partial power down and total power down choices.
Programmable Build-in Self Test (BIST) makes memory testing almost
transparent and reduces production costs.
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Technology
