|
|
 |
|
|
 |
TSMC Reference Flow 10.0 |
|
|
 |
|
| |
Reference Flow 10.0 Supports TSMC's Most Advanced Process Technology with
Advanced Features address New Design Challenges at 28 Nanometer |
TSMC introduced the industry's first Reference Flow in 2001. The company has since
established Reference Flow as a new foundry design service standard, and continues
to enhance its Reference Flow capabilities. The result is the most comprehensive
portfolio, featuring nine consecutive releases enabling designers to design in
TSMC's advanced technologies.
As the foundry industry design methodology leader, TSMC raises the bar by
addressing the most critical design challenges today with Reference Flow 10.0,
one of the key collaborative components of the TSMC Open Innovation
PlatformTM.
The newest generation of the company's Reference Flow continues the tradition
of driving advances in design methodology, addresses new design challenges of
28nm process technology, including a differentiated set of new power management
techniques, improved statistical static timing analysis methodology, and array
of design for manufacturing (DFM) enhancements, and delivers innovations to
enable System-in-Package (SiP) design to lower design obstacles, reduce power
consumption, improve design margins and maximize yield. |
|
| 28nm Design Enablement |
| TSMC's Open Innovation Platform (OIP) paves
the way for EDA tools to be ready for 28nm process technology. OIP enables design
and process technology co-optimization in the early stage of R&D, and ensures
required EDA tool enhancements to happen correctly and timely. Specifically for
Reference Flow 10.0, TSMC went beyond physical verification of DRC, LVS and
extraction that heavily depend upon 28nm process requirements, and engaged
early with EDA partners to qualify their place and route tools for TSMC 28nm.
|
| System in Package (SiP) |
|
System-on-Chip (SoC) has been the focus in the previous nine generations
of the TSMC Reference Flow starting in 2001. Reference Flow 10.0 introduces
SiP design solutions for the first time including SiP package design, electrical
analysis of package extraction, timing, signal integrity, IR drop, and thermal
to physical verification of DRC and LVS. These SiP technologies enable customers
to explore their implementation and integration strategies, realize end product
design and strengthen competitive advantages in terms of cost, performance, and
time-to-market.
|
| Differentiated Features in Power, Performance and DFM |
New low power features in Reference Flow 10.0 include support for pulsed
latch, a new low-power implementation scheme for power saving, and hierarchical
low power automation, multi-corner power/timing co-optimization, multi-corner
low power Clock Tree Synthesis (CTS), vectorless power analysis and more,
enabling more effective power-aware implementation and power analysis. To
drive greater performance, advanced stage-based On-Chip Variation (OCV)
optimization and analysis is made available for the first time, enabling
customers to get a more realistic look at timing for the purpose of removing
redundant design margins. A new electrical DFM feature is introduced for
customers to take into consideration the timing impact of "silicon stress
effect," thus helping to increase yields.
|
| Log In to TSMC-OnlineTM |
| Need further information about
TSMC Reference Flow? Please log
in to TSMC-OnlineTM, and click
on "Reference Flow" under the Design Portal 2.0 category.
Please contact Andrew Wu (email address: andrew_wu@tsmc.com
) should you have questions, suggestions, and comments.
|
|
|
|
Services
