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CoWoS® Services    
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TSMC CoWoS® (Chip-On-Wafer-On-Substrate) services use Through Silicon Via (TSV) technology to integrate multiple chips into a single device. This architecture provides higher density interconnects, decreases global interconnect length, and lightens associated RC loading resulting in enhanced performance and reduced power consumption on a smaller form factor. The convergence of the IC package and the system board into a single system package minimizes the number of packages on a board.
CoWoS® also allows designers to partition large die into smaller ones or partition subsystems by packaging multiple chips manufactured on different process technologies into one device. For example, a designer may choose an advanced technology for critical parts, such as CPUs, and use mainstream technology alongside it to optimize cost.


TSMC offers an integrated CoWoS® manufacturing service that drives shorter time-to-market through streamlined one-stop backend services and close alliances with ecosystem partners.

TSMC CoWoS® Benefits:

Fully integrated 300mm capability, TSV, micro-bump, solder bump, backside processes and assembly.
An advanced silicon metal scheme for improved interconnect and routing density.
Integrated design infrastructure that includes PDK, design flow and a test methodology through collaboration with ecosystem partners.

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TSMC Files Annual Report on Form 20-F for 2016(2017/04/13)
   
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