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TSMC's innovative CoWoS® advanced packaging technology integrates logic computing and memory chips in a 3-D way for advanced products targeting artificial intelligence, cloud computing, data center, and super computer applications. This revolutionary 3-D integration facilitates power-efficient high speed computing while reducing heat and CO2 emissions.

In 2012, TSMC successfully used CoWoS® to integrate four 28nm chips, providing customers high-performance FPGA components with the shortest time-to-market. In 2014, TSMC produced the world's first 16-nm three-chip integrated device with networking capabilities using CoWoS® technology.

Then in 2015, TSMC developed and qualified a super large interposer (greater than 32mm x 26mm) using CoWoS-XL technology. This process integrates multiple large advanced chips on a single CoWoS® module. The productions in 2016 and 2017 include an FPGA with 20nm multi-chip structure and super-high performance computing chips that integrated a 16nm SoC with a next generation HBM2 DRAM. Currently, TSMC is developing a 7nm CoWoS® advanced packaging technology.
TSMC May 2018 Revenue Report(2018/06/08)
TSMC Sets June 25 as Ex-Dividend Date(2018/06/06)
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