With over a decade of collaboration with EDAs as basis, TSMC Reference Flow provided extensive and comprehensive design solutions. To secure TSMC’s long term commitment to customers on providing high-quality design solutions, TSMC makes available two reference flows this year, targeting at the most advanced technologies of 20nm SoC and CoWoS respectively.
Reference Flow 20nm
TSMC’s first double patterning (DPT) aware design flow addressing 20nm design challenges which is built on top of N20 EDA Certification Program to enable DPT technology compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM) solutions.
Reference Flow’s transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20nm design flow setup and learning curve, and accelerates 20nm process adoption.
Reference Flow CoWoS
TSMC’s first integrated and validated design flow addressing emerging problems of 3D IC multi-die integration accurate extraction and signal integrity analysis of high-speed interconnections, thermal analysis from chip to package to system, and integrated 3D testing methodology for die-level and stacking-level tests.
CoWoS Reference Flow enables smooth transition from 2D IC to stacking design with minimal changes to existing design methodology while achieving performance, power and form factor goal.
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