Reference Flow™ 12.0 Completes TSMC's 28nm Design Infrastructure
Design Challenges
TSMC introduced the foundry segment's first Reference Flow in 2001. The company has since established its Reference Flow as a foundry design service standard and continues to enhance its capabilities. The result is the most comprehensive Reference Flow portfolio that encompasses 12 consecutive releases..
As the foundry design methodology leader, TSMC addresses the most critical design challenges through Reference Flow™ 12.0, furthering its tradition of driving advances in design methodology and completing TSMC’s 28nm design infrastructure. Reference Flow 12.0 features various enhancements in integrated circuits using silicon interposer and through silicon via (TSV) technologies; 28nm model-based simulation, increased DFM speed; and advanced Electronic System Level (ESL) design initiative enabling TSMC’s process technology PPA (power, performance, and area) to be integrated into system-level design. In addition, Reference Flow 12.0 discloses TSMC’s 20nm Transparent Double Patterning design solution as part of the on-going effort to build up 20nm design capability within OIP.
The flow is one of the key collaborative components of TSMC’s Open Innovation Platform that accelerates time-to-market, improves return on design investment and reduces design infrastructure duplication.
Extensive EDA partner collaboration is the hallmark of TSMC’s Reference Flow, offering advanced design methodologies through collaboration with 18 EDA partners – for high value, low risk and easy adoption of TSMC process technology.
Reference Flow 12.0 and Transparent Double Patterning for 20nm
20nm is the first process node where metal pitch is beyond the lithographic capabilities of existing exposure systems. Double patterning is the key enabling lithographic technology to overcome the litho resolution limitations without resorting to as yet production unproven technologies as EUV. TSMC’s Transparent Double Patterning solution enables system and chip designers to access 20nm technology, implemented with double patterning, without any modifications to their current design methodologies or flows. This technology is being delivered to EDA partners and certified for delivery in their commercial products.
Silicon Interposer
A silicon interposer design includes multiple dies, logic, memory and/or analog/mixed-signal, integrated side-by-side on a silicon interposer, which is implemented in different technology. Reference Flow 12.0 features new design capabilities in floorplanning, P&R, and IR-drop and thermal analysis to accommodate multiple process nodes simultaneously, as well as a new design for test methodology for silicon interposer design.
28nm Power, Performance and DFM Design Enablement
Timing degradation from wire and via resistance becomes more significant in finer geometry technologies: Reference Flow 12.0 introduces an enhanced routing methodology to minimize via counts, change layers for routing, or widen wires to mitigate the impact of wire and via resistance.
Leakage current increases as threshold voltage and gate oxide thickness decrease in 28nm. Multi-Mode Multi-Corner (MMMC) leakage optimization accommodates different Vt options and gate-biased libraries enabling designers to more effectively reduce leakage.
Finally, in order to minimize the design cycle time of hotspot checking and fixing in 28nm, a new “hotspot filtering engine” is added to the DFM Data Kit (DDK) to speed up model-based DFM analysis.
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