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TSMC Reference Flow™    
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TSMC has been collaborating with EDA Alliance members since 2001 to develop design methodology innovations that boost & optimize design power, performance and area (PPA) and streamline overall design flow through combined resource and capabilities for the purpose of reducing design iterations, and help customers in design cost saving and shorten time-to-market cycle time.

The design reference flows cover Digital, Custom and 3DIC Stacking design solutions to address the most recent market demands and design challenges in the advanced nodes.

The 3DIC process provides significant silicon scaling, power and performance benefits by integrating multiple components on a single device. TSMC’s 3DIC Reference Flow addresses emerging integration challenges through different 3D package schemes with the rollout of CoWoS® and InFO (Integrated Fan-Out) reference flows.

The illustration below shows the accumulated reference flow solutions that have been rolled out annually.

TSMC May 2018 Revenue Report(2018/06/08)
TSMC Sets June 25 as Ex-Dividend Date(2018/06/06)
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