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Wafer Bumping Services    
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TSMC offers various leading edge wafer bumping processes:

Bump Material Eutectic Lead Free Cu
Bump Composition (Plated) PbSn SnAg Cu /SnAg Cap
Adv. Si node (Qualified) 28nm 28nm 28nm
Available Wafer Sizes 12" 12" 12"
Max. Chip Size (mm2) <650 <400 <225
(<650 in 2H'13)
Min. Bump Pitch (um) 150 140 80
Re-distribution layer Yes Yes Yes
Polyimide Yes Yes Yes
Wafer Thickness (mil) ≥29 (FCBGA) 4~12 (FCCSP)
≥29 (FCBGA)
4~12 (FCCSP)
≥29 (FCBGA)
EM Performance
(max current density per bump)
1X 1.2X 2X
Environmental Friendliness No Yes Yes

TSMC Bumping Service Benefits:

TSMC's chip-to-package process interaction assessment saves months on flip chip technology development.
Capacity Management
TSMC's integrated operation streamlines planning and simplifies supply chain management.
Cycle time Control
TSMC has built a reputation for integrating wafer and bumping processes to fit multiple outsource assembly and test (OSAT) strategies.
TSMC April 2017 Revenue Report(2017/05/10)
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