TSMC's 55nm process is a 90% linear shrink process from the 65nm process. It provides cost savings while maintaining the same speed with similar or lower power. The 55nm logic family includes General Purpose (GP) and Low Power (LP) options. Both of these two processes have SPICE model, standard cell, memory compiler and critical IP support so that designers can access 55nm technology just as they would any full node process. Designers can easily shrink 65nm products with minimum re-characterization.