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The 65nm process offers cost-effective benefits superior to the 90nm node. It features twice the gate density and boasts a speed improvement of between 30 to 50 percent. The 65nm process also provides the smallest SRAM cell and reduces power with a multiple Vt architecture and other process innovation.

TSMC's 65nm logic family includes General Purpose (GP), Low Power (LP), Ultra-Low Power (ULP) and LPG options. Each process supports low, standard, and high Vt options. Operating voltages range from 0.9V to 1.26V. I/O voltages include 1.8V, 2.5V and 3.3V (5V tolerant). Raw gate density is around 854 Kgate/mm2, based on TSMC's standard cell library. SRAM cells range from 0.499μm2 (6T) to 1.158μm2 (8T).

The 65nm process provides a combination of General Purpose (G) and Low Power (LP) core transistors together with a 2.5V I/O transistor as a Triple Gate Oxide (LPG) process for optimizing speed, power, and leakage for wireless/consumer applications.

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