Services
Home > Services > Design > Design Implementation Services
 
TSMC-Online
Contact Us
Search

Sarnoff Europe
Overview

Sarnoff Europe provides ESD DESIGN SOLUTIONS for standard and HV CMOS processes. We license ESD protections that are product proven from 0.5um to 65nm technology. We integrate ESD design in your IO, your custom interface, your power grid… to your specifications. For clients with multiple IC per process per year plans, we offer an attractive ESD design tool set, including GDSII and a calculation tool.

Sarnoff Europe’s ESD solutions are marketed under the TakeCharge® portfolio brand. We offer state-of-the-art ESD design expertise to meet the design challenges of today’s complex and/or demanding IC design requirements. Our extensive portfolio covers specialty solutions for SerDes, HDMI, RF and HV applications. Our 45nm solutions are nearing completion.

Using Sarnoff scalable solutions, customers can reach any ESD specification (e.g. the new 8kV HBM standard for HDMI) without compromising full IC functionality at high communication speeds. MM and CDM specifications are also covered by the TakeCharge ESD solution set.

Sarnoff Europe has created a full set of design flow, integration and calculation tools combined in its TakeCharge Design Kit. We empower our customers with solutions, tools and knowledge to independently implement ESD design as part of their overall IC design. TakeCharge provides both IO and full chip ESD protection strategies for all types of IC’s – including those with multi-power domains – combined with dedicated training for customer design and layout engineers.

The Sarnoff engineering team is ready to support all customer requests and provide design review services prior to product tape-out. After all, from an industry leader, you are entitled to a superior service above and beyond your expectations.

.

Design Service Portfolio
  Our vision:
 
ENABLE OUR CUSTOMERS TO INDEPENDENTLY PERFORM SUCCESSFUL FIRST-TIME-RIGHT ESD DESIGN FOR ALL IC’s.
  ESD Design Services
 
TAKECHARGE DESIGN KIT
 
Complete solution set for IO and full-chip ESD protection, including GDSII
Integration tools : design flow – calculation tool – integration tool
Detailed documentation regarding ESD protection, design, layout, strategies with integration guidelines

Training for design and layout engineers to enable successful first-time-right and independent implementation
ESD design support and review available by our engineering teams
TAKECHARGE DESIGN SOLUTIONS
 
Fast turnaround : +/- 3 weeks
Full delivery of solution set for single chip
Includes review prior to tape-out
TAKECHARGE DESIGN SUPPORT AND REVIEW
 
Available for all customers
Support packages tailored to individual customer needs
“get the chip on the market”
 
  ESD Design Successes
 

More than 40 processes covered
In 2007:

 
125 commercial products using TakeCharge released by our customers
80 high volume products commercially released at 130nm and below
19 high volume products released in 65nm
* Training for design and layout engineers to enable successful first-time-right and independent implementation
* ESD design support and review available by our engineering teams
  Intellectual Property
 

Solutions for all protection strategies and needs :

 
IO : general – high speed – RF – differential/LVDS
Power protection – input protection – output driver protection
Overvoltage tolerant solutions
Analog solutions
IC with multiple power domains
  IP Portfolio
 
ESD on-chip protection design solutions – covered by more than 50 patents. Clean portfolio.
 
  Contact Information
 
Headquarters Address:
 
Sarnoff Europe BVBA
Brugsebaan 188A
B-8470 GISTEL
Belgium
Contact Persons:
 
For business information : Katty Van Mele
For technical information : Bart Keppens
Phone : +32 59 275 915
Fax : +32 59 275 916
Email : tsmc.dcaservices@sarnoffeurope.com
Corporate Website
http://www.sarnoffeurope.com