Home > TSMC 2013 Open Innovation Platform® Ecosystem Forum Technical Papers > Design Reliability with Calibre® YE-SmartFill and Calibre® PERC™ (Broadcom & Mentor Graphics)
Design Reliability with Calibre® YE-SmartFill and Calibre® PERC™ (Broadcom & Mentor Graphics)    
IP Technical Presentations
EDA Technical Presentations
Managing Wire Resistance, Cell Pin Access and FinFET Parasitics at TSMC 16nm Using Cadence Place & Route and RC Extraction Technologies (Cadence)
Design Reliability with Calibre® YE-SmartFill and Calibre® PERC™ (Broadcom & Mentor Graphics)
TSMC 16nm FinFET SRAM Design Verification (Synopsys)
Addressing Custom Design Challenges for IP Design at 16nm FinFET technology (Cadence)
A Synergetic, Multi-Partner, Soft Error Rate Analysis Framework for Latest Process Nodes (iROC)
EDA-Based DFT for 3D-IC Applications (Mentor Graphics)
Advanced Power, Signal and Reliability Verification for 20nm, 16nm FinFET, and 3D-IC Designs (ANSYS Apache)
Low Power, Faster Timing ECO for Sub-20nm Designs (Dorado Design Automation)
FinFET Modeling and Extraction for 16-nm Process (Synopsys)
Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & nVIDIA)
Design and Implementation of High Resolution 60GHz PLLS and DCOs Using the EMX 3D EM Simulator (Integrand Software)
An Efficient and Accurate Sign-Off Simulation Methodology for High-Performance CMOS Image Sensors (Berkeley Design Automation & Forza Silicon)
Design and Modeling Platform for the TSMC's FOWLP Reference Design Kit (Agilent)
Synopsys Laker Custom Layout and Calibre Interfaces: Putting Calibre Confidence in Your Custom Design Flow (Mentor Graphics)
Circuit Reliability Simulation with TSMC TMI Age Model (Cadence)
Design Service Technical Presentations
Print-Only Technical Presentations
 
Abstract:

The complexity of advanced technologies drives new requirements for poly/OD and metal fill to solve critical manufacturing effects, and more importantly design yields. New methodologies were developed for 28nm designs using Calibre SmartFill to meet the new strict DFM requirements while reducing run time, file size and iterations.

Besides manufacturing process, electrical rule checks can also significantly impact design yields & reliability. Identifying incorrectly configured devices, multi-power domain transition guides, and floating (leaky) gates is critically important right from the circuit stage, well before physical layouts. Such early design consistency checks written with rules in Calibre® PERC™ help us catch design mistakes early on, and validate some of our high reliability design metrics.

Both Calibre Smart-Fill and Calibre® PERC™ were significantly and successfully deployed on Broadcom's largest 28nm tapeout recently, which the Broadcom representative will describe in the presentation.


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