Home > TSMC 2013 Open Innovation Platform® Ecosystem Forum Technical Papers > Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & nVIDIA)
Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & nVIDIA)    
IP Technical Presentations
EDA Technical Presentations
Managing Wire Resistance, Cell Pin Access and FinFET Parasitics at TSMC 16nm Using Cadence Place & Route and RC Extraction Technologies (Cadence)
Design Reliability with Calibre® YE-SmartFill and Calibre® PERC™ (Broadcom & Mentor Graphics)
TSMC 16nm FinFET SRAM Design Verification (Synopsys)
Addressing Custom Design Challenges for IP Design at 16nm FinFET technology (Cadence)
A Synergetic, Multi-Partner, Soft Error Rate Analysis Framework for Latest Process Nodes (iROC)
EDA-Based DFT for 3D-IC Applications (Mentor Graphics)
Advanced Power, Signal and Reliability Verification for 20nm, 16nm FinFET, and 3D-IC Designs (ANSYS Apache)
Low Power, Faster Timing ECO for Sub-20nm Designs (Dorado Design Automation)
FinFET Modeling and Extraction for 16-nm Process (Synopsys)
Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & nVIDIA)
Design and Implementation of High Resolution 60GHz PLLS and DCOs Using the EMX 3D EM Simulator (Integrand Software)
An Efficient and Accurate Sign-Off Simulation Methodology for High-Performance CMOS Image Sensors (Berkeley Design Automation & Forza Silicon)
Design and Modeling Platform for the TSMC's FOWLP Reference Design Kit (Agilent)
Synopsys Laker Custom Layout and Calibre Interfaces: Putting Calibre Confidence in Your Custom Design Flow (Mentor Graphics)
Circuit Reliability Simulation with TSMC TMI Age Model (Cadence)
Design Service Technical Presentations
Print-Only Technical Presentations

Today, top level chip assembly and optimization is a highly iterative and manual process that can have a huge impact on design turn-around time and QoR. At advanced nodes, this problem is getting exacerbated due to the dramatic increase in the number of available transistors and increasing variability. In this session Mentor and nVidia will discuss the chip assembly and design closure solution for TSMC processes. Technology highlights include concurrent MCMM optimization, synchronous handling of replicated partitions and layer promotion of critical nets for addressing variation in resistance across layers.

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