Hsinchu, Taiwan, R.O.C. - March 27, 2007 - Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) today unveiled its 55nm process technology, a 90% linear-shrink process from 65nm including I/O and analog circuits. The process delivers significant die cost savings from 65nm, while offering the same speed and 10 to 20% lower power consumption. Because the 55nm process is a direct shrink, IP providers can leverage existing libraries and port their 65nm designs with minimal risk and effort. The 55nm logic family includes general purpose (GP) and consumer (GC) platforms. Initial production of the 55GP begins this quarter, followed later in the year by 55GC.
While TSMC has already engaged many leading customers and IP suppliers on the process, the company will continue to streamline adoption using its CyberShuttle prototyping program that allows multiple customers and IP suppliers to share the costs of a single mask set and prototype wafers on a pilot run. The 55nm CyberShuttle runs are expected to be offered on a bi-monthly basis starting from the beginning of May this year.
“TSMC’s half-node process, including 55nm, is the quickest and simplest way for our customers to be cost competitive in the rapidly changing marketplace,” said Jason Chen, vice president of corporate development of TSMC. “TSMC continues to combine manufacturing superiority with a comprehensive design ecosystem to support customers of any size, from startups to multinational giants.”
TSMC’s half-node strategy has a proven track record of helping customers achieve a crucial edge in a fiercely competitive marketplace. The company has been offering half-node processes for six technology generations starting from 0.35-micron.