Hsinchu, Taiwan, R.O.C. – November 17, 2008 - TSMC (TSE: 2330, NYSE: TSM) today announced volume production of the first semiconductor foundry 40nm logic manufacturing process with the successful ramp of its 40 nanometer (nm) General Purpose (G) and Low Power (LP) versions. Nanometers measure the width of metal lines in semiconductors. Forty nanometers is less than one-thousandth the width of a human hair.
The 40nm process is one of the semiconductor industry’s most advanced available for production manufacturing process and is expected to play a key role in the development of next generation products in global consumer electronics, mobile, and computer end markets.
“For decades, IDMs set the pace for innovation in process technology and services,” said Kay-Yang Tan, Gartner Dataquest principal research analyst, said. “They will continue to play a significant role in fostering new products, but dedicated foundries, such as TSMC, have become key contributors to next generation products that will drive the eventual resurgence of the worldwide semiconductor industry.”
According to Gartner, foundry contribution of chips sold to the global semiconductor market has over the past decade increased from 9.2% in 1998 to 25.3% in 2008.
“We view 40nm as an important process node for the cost-effective development of graphics chips and other devices, especially in 2009. This is another example of a long and successful history of AMD and TSMC ramping leading edge processes,” said Rick Bergman, Senior Vice-President & General Manager, Graphics Products Group.
“Today designers are faced with the challenge of increasing the functionality of their product while not increasing power consumption. By rolling out the industry’s most advanced programmable logic devices at 40-nm, we are enabling designers to quickly achieve new levels of integration and innovation, while staying within their power budgets,” said Bill Hata, Altera senior vice president of Worldwide Operations and Engineering.
TSMC’s 40nm G and the 40nm low power (LP) manufacturing processes timetables were formally announced in March this year. The 40G process targets performance-driven applications including computer processor chips, GPU (graphic processing units), game consoles, networking applications, field programmable gate arrays (FPGA), hard disc drive, and other devices. The 40LP process targets low-power applications including cellular baseband, application processors, portable consumer and wireless connectivity devices.
"High-performance GPUs are only continuing to grow in importance for a variety of industries," said Debora Shoquist, NVIDIA senior vice president of Operations. "The advantages that TSMC's 40nm G process provides to designing a GPU will allow us to continue pushing the limits of what's currently possible."
TSMC’s 40nmG and 40nm LP processes both passed process qualification, reaching “first wafers out” status as planned and completed product qualification in October when first customer wafers entered production. As with every TSMC process node, the 40G and 40LP processes offer a full range of mixed-signal and RF options, along with embedded memory to support a broad range of analogy/RF-intensive and memory-rich applications.
”While timed to respond to the technical requirements of our broad customer base, the two processes are clearly the right manufacturing processes at the right time and can help stimulate the semiconductor industry to produce the next wave of new products,” said Jason Chen, TSMC vice president, Worldwide Sales and Marketing.