Hsinchu, Taiwan – June 7, 2010
– Taiwan Semiconductor Manufacturing Company, Ltd. (TWSE: 2330, NYSE: TSM) today extended its Open Innovation Platform™ with another focus on system-level design, analog/mixed-signal (AMS)/RF design and two-dimensional/three-dimensional integrated circuit (2-D/3-D IC) implementation. At the same time the company introduced the first three initiatives from the new focus.
TSMC originally launched the Open Innovation Platform in 2008 as an industry-wide design enablement initiative. To date, the Open Innovation platform has accelerated time-to-market, improved return on design investment and reduced design infrastructure duplication. It includes a set of interoperable ecosystem interfaces, collaborative components and design flows that efficiently empower innovation throughout the supply chain thereby enabling creation and sharing of newly-created revenue and profitability. For example, iPDK, iDRC, iLVS, iRCX, Digital Reference Flow, Integrated Signoff Flow and RF Reference Design Kit are all in production use today.
“TSMC’s Open Innovation Platform delivers comprehensive and innovative design technology services that remove advanced technology adoption barriers. It helps lower design costs and improves time-to-market,” said Dr Fu-Chieh Hsu, Vice President of Design Technology Platform and Deputy Head of Research & Development. “The Open Innovation Platform will now begin addressing system-level design’s cost and complexity and enable packaging of entire electronic systems onto multi-chip packages.”
Open Innovation Platform Roadmap Update
The Open Innovation Platform will extend beyond power, performance and area considerations (PPA) and interoperability initiatives to feature new collaborative ecosystem programs that focus on electronic-system level (ESL) design, virtual platforms and high-level synthesis (HLS). Other new programs will address 65nm, 40nm and 28nm analog, mixed-signal and RF design methodologies while a third direction tackles multi-die packaging through 2-D/3-D IC design methodology, innovative silicon interposer and through silicon via (TSV) manufacturing capabilities.
The Open Innovation Platform’s Alliance programs collaborate with EDA, IP, software IP, systems software and design services partners. The objectives are to deliver accelerated system-level design, reduced system design cost, a faster system-to-IC implementation design cycle, and faster time-to-market.
“The design ecosystem must move beyond its current bounds and embrace the systems- level challenges that are at the heart of every design consideration. The Open Innovation Platform began setting the standard for ecosystem collaboration two years ago. TSMC continues to answer the market’s call and will build that same collaborative spirit on a system-level basis,” explained S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.
The Open Innovation Platform’s global Ecosystem Alliance programs have grown to include 30 EDA partners, 38 IP partners, 23 Design Center Alliance (DCA) partners, and 9 Value Chain Aggregator (VCA) partners. All partners participate in one or more of the Open Innovation Platform collaboration programs. TSMC also begins to work collaboratively with industry organizations, such as IPL Alliance and Si2, to promote the interoperability standards based on TSMC interoperable EDA formats.
Three New Initiatives
TSMC is introducing Radio Frequency Reference Design Kit (RF RDK) as an outgrowth of an extended Open Innovation Platform and will shortly announce the availability of Analog/Mixed-Signal (AMS) Reference Flow 1.0, Reference Flow 11.0.
Radio Frequency Reference Design Kit (RF RDK) 2.0 targets TSMC’s 65nm RF CMOS process technology, accelerating analog, mixed-signal, and RF designs and RF System-on-Chip (SoC) verification and integration. It resolves the long-standing challenge of performing full chip verification on SoC devices that support analog, RF, mixed signal and digital content.
The new design kits implement a top-down RF design methodology and a system-level simulation flow that reduces design cycle time and encourages IP reuse. The RF RDK 2.0 is in Open Access database that supports new RF design capabilities including a circuit sizing and design centering approach, electromagnetic (EM)-aware RF simulation and analysis, custom RF inductor synthesis and modeling, and substrate noise modeling and analysis (SNA) to address the noise coupling challenges in complex mixed-signal and RF SoCs.
Design Community Weighs In
Reaction to TSMC’s extension of Open Innovation Platform has met with wide acceptance from main design community providers.
“The electronic design community is embracing the EDA360 vision to enable fastest approach from concept to consumer and together with IP suppliers, EDA vendors and silicon manufacturers, we have diligently collaborated to build a cohesive path for designers,” said Lip-Bu Tan, president and chief executive officer, Cadence. “TSMC’s Open Innovation Platform is a proven, integral part of this path. TSMC’s Open Innovation Platform will now make significant advancements in low-power, mixed-signal, system-level and 3D-IC design to enable further productivity improvements that our mutual customers need.”
“Going forward, Mentor and TSMC are developing complete solutions for the TSMC design ecosystem, ” said Walden C. Rhines, Chairman and CEO, Mentor Graphics. “The TSMC OIP effort is not just words — the Mentor Track in Reference Flow 11.0, and the co-developed iDRC and iLVS languages, are real usable results.”
“Collaboration across the entire design eco-system — customers, foundries, IP and EDA suppliers — is critical for lower design risk and cost, better power and performance, and customer differentiation, ” said Aart de Geus, Chairman and CEO, Synopsys. “The new technologies in this phase of TSMC OIP, such as system-level design, analog/mixed-signal (AMS) design and thru-silicon-via, bring key solutions to speed System-to-IC realization.”
TSMC is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. The Company’s managed capacity in 2009 totaled 9.96 million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GIGAFABs™, four eight-inch fabs, one six-inch fab, as well as TSMC’s wholly owned subsidiaries, WaferTech and TSMC China, and its joint venture fab, SSMC. TSMC is the first foundry to provide 40nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.