TSMC's front-end 3D SoIC™ is a key technology pillar to advance the field of heterogeneous chiplets integration with reduced size, increased performance. It features ultra-high-density-vertical stacking for high performance, low power, and min RLC( resistance-inductance-capacitance). SoIC integrates active and passive chips into a new integrated-SoC system, which is electrically identical to native SoC, to achieve better form factor and performance.
The key features of SoIC include:
Enables the heterogeneous integration (HI) of known good dies (KGDs) with different chip sizes, functionalities and wafer node technologies.
(a) SoC before chip partition; (b), (c), (d) Variant partitioned chiplets and re-integrated schemes enabled by SoIC
With the innovative bonding scheme, SoIC enables the strong bonding pitch scalability for chip I/O to realize a high density die-to-die interconnects. The bond pitch starts from sub-10 µm rule. Short die-to-die connection of SoIC has the merits of smaller form-factor, higher bandwidth, better power integrity (PI), signal integrity (SI), and lower power consumption comparing to the current industry state-of-the-art packaging solutions.
Holistic 3D System Integration
SoIC integrates both homogeneous and heterogeneous chiplets into a single SoC-like chip with a smaller footprint and thinner profile, which can be holistically integrated into advanced WLSI (aka CoWoS and InFO ). From external appearance, the SoIC is just like a general SoC chip yet embedded with desired and heterogeneously integrated functionalities
(a) CoWoS with SoC, (b) CoWoS with SoIC, (c) InFO_PoP with SoC, (d) InFO_PoP with SoIC