Annual Reports  >  2013  >  Operational Highlights > Technology Leadership
Technology Leadership
繁中

R&D Organization and Investment

In 2013, TSMC continued to invest in R&D with total R&D expenditure amounting to 8% of revenue, a level that equals or exceeds the R&D investment of many other high technology leaders. Along with the increase in budget, R&D staffing increased by 11%.

Amount: NT$ thousands

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TSMC recognizes that the technology challenge required to extend Moore’s Law, the business law behind CMOS scaling, is becoming increasingly complex. The efforts of the R&D organization are focused on enabling the Company to continuously offer its customers first-to-market, leading edge technologies and design solutions that contribute to their product success in today’s complex and challenging market environment. In 2013 the R&D organization met these challenges by introducing into manufacture the industry-leading 20nm technology. The 16nm technology, which is the first integrated technology platform to make use of 3D FinFET transistors, has also met its development goals and is now in risk production. The R&D organization continues to strengthen the pipeline of technology innovations that are required to maintain technology leadership. The 10nm technology advanced development was completed, and entered full development, while the 7nm technology is in the early development stage.

In addition to CMOS logic, TSMC conducts research and development on a wide range of other semiconductor technologies that provide the functionality our customers require for mobile SoC and other applications. Highlights achieved in 2013 include: production ramp of the CoWoS™ (Chip on Wafer on Substrate) 3D packaging technology; extension of the 28nm technology for RF and embedded flash technologies; the first industry introduction of the BCD power technology into a 12-inch fab environment and, manufacturing readiness of TSMC’s first wide band gap Gallium Nitride (GaN) semiconductor technology for high frequency power applications.

TSMC maintains a network of important external R&D partnerships and alliances with world-class research institutions such as IMEC, the respected European R&D consortium, where TSMC is a core partner. TSMC also provides funding for nanotechnology research at leading universities worldwide to promote innovation and the advancement of nanoelectronic technology. In 2013, TSMC announced the formation of collaborative research centers with National Taiwan University and National Chiao Tung University in Taiwan, and anticipates announcing the establishment of additional research centers in Taiwan in 2014.

R&D Accomplishments in 2013

R&D Highlights

  • 28nm Technology

TSMC delivered the world’s first 28nm High-k/Metal Gate triple gate oxide technology (28HPT). This technology provides 10% faster speed compared to the 28HPM technology while keeping the same leakage power. 28HPT is qualified for production in both Fab 12 and Fab 15 with equivalent yield to 28HPM.

  • 20nm Technology

TSMC’s 20nm technology was successfully qualified for volume manufacture.

  • 16nm Technology

The 16nm technology features FinFET transistors with a third generation High-k/Metal Gate process, a fifth generation of transistor strain process, and advanced 193nm lithography. FinFET transistors offer substantial power reduction at the same chip performance compared to transistors built with the traditional planar structure, which is essential for advanced mobile applications. In 2013, the R&D organization successfully verified the process development test vehicle (TV1R), provided customers with version 1.0 design kits (design rules and SPICE models) and offered two public cyber shuttles. More than 10 customers and IP vendors took the shuttles and verified their IP. The 16nm technology has completed manufacturing qualification with good yield.

  • 10nm Technology

2013 saw the introduction of 10nm technology into development. The 10nm technology will offer substantial power reduction for the same chip performance compared to earlier technology generations. Development activities in 2014 will focus on manufacturing baseline process setup, yield learning, transistor performance improvement, and reliability evaluation. TSMC plans to enter 10nm risk production in 2015 and volume production in 2016.

  • Lithography

2013 was a productive year in 16nm lithography development with the technology reaching the risk production stage. Several novel patterning techniques were developed for 48nm pitch Fin patterning. These techniques overcame the challenge of high aspect ratio topography of 3D device structures. Besides patterning challenges, defect reduction on the high aspect ratio topography also required special engineering efforts. Several key solutions were developed in 2013, such as improvement in tool and process recipe co-optimization, and enhanced defect-monitoring methodology. The development of optimum automation and Advanced Process Control systems, including enhanced tool control and stability, resulted in significant reduction of rework rate and cycle time, helping to drive faster learning in both defect reduction and yield improvement.

Several new techniques were introduced during 2013 to enable the successful launch of 10nm development. While the immersion lithography process will be extended to the 10nm node, the double patterning technique that was developed for the 20nm and 16nm nodes is insufficient to meet 10nm requirements. Multiple patterning becomes essential to enable high yield manufacturing. To further stretch the patterning capability of optical lithography, significant learning in material processing, image modeling, and defect control has been achieved to make the 10nm process viable.

In 2013, TSMC took delivery of a NXE3300 extreme ultraviolet (EUV) scanner, and exposed its first wafers after successful installation. While we see a clear advantage in process simplification by the use of EUV as opposed to multiple patterning with optical immersion lithography, insufficient power of the EUV light source is our major concern.

Multiple e-beam direct-write lithography (MEB DW) not only has the potential for economical imaging critical layers, but it also may offer cost reduction potential for non-critical layers and 450-mm wafers. It is being developed to meet the need of 7nm node imaging and beyond. A TSMC team from the design, CMOS, MEMS, and packaging areas is jointly developing and fabricating the digital pattern generation (DPG) module for the Reflective E-Beam Lithography (REBL) system of KLA-Tencor. The first DPG test chip, which was a collaborative effort between TSMC and KLA-Tencor, was taped out in the third quarter of 2013.

  • Mask Technology

Mask technology is an integral part of our advanced lithography. In 2013, we completed the development of mask technology for the 16nm node and made solid progress on development for the 10nm node. In the meantime, continued progress is being made on the mask technology for EUV lithography. Working with suppliers, we continue to drive down counts of native defects on mask blanks. In addition TSMC continues to work with several industrial consortia in developing the infrastructure of EUV mask technology.

Integrated Interconnect and Packaging

  • 3D IC

TSMC achieved a new industry landmark in 2013 with the ramp up to volume production of a new turnkey system integration solution called CoWoS™. The CoWoS™ solution is integrated with TSMC’s advanced silicon technologies to provide customers with alternatives for system level integration compared to the traditional SoC approach. The technology has passed customer product qualifications with 28nm FPGA products. At 20nm, development continues and we expect customer tape outs in the first half of 2014. We successfully demonstrated 3D IC stacking of an application processor and wide I/O DRAM in 28HPM technology through transistor stacking (TTS) TSV technology, and completed 16nm TSV process development.

  • Advanced Package Development

TSMC offers a wide variety of lead-free flip chip packaging technologies. In 2013, TSMC qualified for manufacture at 20nm an innovative Bump-on-Trace (BoT) packaging technology with an ultra-fine pitch (80µm) copper (Cu) bump that is suitable for mobile/ handheld devices. Additionally, lead-free flip chip packaging was enhanced for ultra large die size (≥600mm2) for high performance applications (GPU/CPU/FPGA/Networking Processor).

  • Advanced Interconnect

Development of low resistance Cu and low capacitance dielectric continued to be the primary focus in 2013. At the 16nm node, a novel dielectric scheme has been developed that reduces the capacitance between copper lines. For the 10nm node and beyond, we have developed a new spacer-patterning scheme that allows copper line width and spacing to be reduced and minimizes signal delay. The effective resistivity of copper lines developed with these advanced processes is highly competitive and is lower than that projected by the International Technology Roadmap for Semiconductors (ITRS).

Advanced Transistor Research

The increased performance and lower power requirements of advanced logic technologies require constant innovation in transistor architecture and materials. TSMC is at the forefront of research in these areas, with particular focus on non-silicon channel materials such as germanium and III-V compounds because of their desirable performance and power characteristics. As an example of the progress being made in this area, our research team recently announced at the 2013 International Electron Devices Meeting world record-breaking transistor performance for both Germanium (Ge) channel PMOS FinFET and Indium Arsenide (InAs) (III-V) channel NMOS. New concepts of transistor structures employing innovative nanotechnology are also under intensive investigation.

Specialty Technologies

TSMC offers a broad mix of technologies to address the wide range of applications that customers are engaged in. The Company enhanced its SoC roadmap to address the needs of specialty applications in mixed-signal, RF markets, high voltage power management IC, high voltage IC’s for display, MEMS and embedded memory.

  • Mixed Signal/Radio Frequency (MS/RF) Technology

TSMC has successfully verified customer products in the 28nm technology for RF CMOS applications (28LP-RF) that are aimed at next generation RF transceivers (e.g. 4G LTE). Higher performance analog and RF solutions are also in development at the 20nm node. TSMC developed and transferred to manufacturing a first generation 0.18µm Complementary Bipolar Complementary MOS (CBCMOS) technology.

  • Power IC/BCD Technology/Panel Drivers

TSMC released the 0.13BCD technology, the first BCD technology to be implemented in a 12-inch fab. The R&D team also completed development and qualified for manufacture the wide band gap material GaN in a high electron mobility transistor (HEMT) configuration for high power, high frequency applications. The 55HV technology was qualified targeting high quality mobile displays, while C015HV was released targeted at the large panel market. TSMC has also developed a 0.18µm HV embedded flash technology for touch panel applications.

  • Micro-electromechanical Systems (MEMS) Technology

A variety of products were qualified for manufacturing ramp in 2013, including products aimed at: giga-level pixel display density; BioMEMS applications such human genome sequencing; second generation motion sensor products; and high-resolution noise cancellation microphones.

  • Flash/Embedded Flash Technology

TSMC achieved several important milestones in embedded flash technologies. At the more mature 65nm/55nm node, NOR based cell technologies including 1-T cell and Split-Gate cell successfully completed customer qualification. At the 40nm node, the split-gate cell technology has been shipped for both automotive and consumer applications. Embedded flash development for the 28LP and 28HPM platforms is underway for low leakage applications such as smartcard, MCU and Automobile.

Technology Platform

TSMC provides our customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time. These include: design flows for electronic design automation (EDA); silicon-proven IP building blocks, such as libraries; and simulation and verification design kits, i.e., process design kits (PDK) and technology files.

To ensure the OIP ecosystem delivers to our customers the highest quality design experience with newly introduced technologies, TSMC has collaborated with our EDA partners to certify EDA tool readiness. In particular, since 16nm is the first FinFET technology for our customers, TSMC and ecosystem partners improved the tool certification process to cover point tool enhancement as well as integrated, cross-tool certification using an advanced CPU core as the vehicle (EDA tool certification results can be found on TSMC-Online).

Given the ever-increasing need for first-time silicon success and early time-to-market for highly integrated circuits, in 2013 TSMC also extended its IP quality program (TSMC9000) to allow IP audits to be performed either at TSMC or at TSMC-certified laboratories. The extended IP quality program currently includes standard interface IP such as MIPI, HDMI and LVDS. Further IP types will be included in the upcoming year. TSMC also donated its IP Tag format to the industry to extend IP quality tracking coverage beyond our IP Alliance partners. To help customers plan new product tape-outs incorporating TSMC certified IP, the OIP ecosystem now features a portal to connect customers to an ecosystem of more than 40 solution providers.

Design Enablement

TSMC’s technology platforms provide a solid foundation for design enablement. Customers can design directly using the Company’s internally developed IP and tools, or using those that are available via our OIP partners.

Tech File and PDK

TSMC provides a broad range of process design kits (PDK) for digital logic, mix-signal, radio frequency (RF), high-voltage driver, CMOS Image Sensor (CIS) and embedded flash technologies across a range of technology nodes from 0.5µm to 16nm. In addition, TSMC provides technology files for: DRC; LVS; RC extraction; automatic place and route; and a layout editor to ensure process technology information is accurately represented in EDA tools. There are more than 100,000 customer downloads of these files every year.

Library and IP

TSMC and its alliance partners offer our customers a rich portfolio of reusable IP, which are essential building blocks for many circuit designs. In 2013, over 60% of new tape-outs at TSMC adopted one or more libraries or IP from TSMC and/or our IP partners. In 2013, TSMC expanded its library and silicon IP portfolio to contain more than 6,300 items, a 16% increase over 2012.

Design Methodology and Flow

In 2013 TSMC addressed the critical design challenges associated with the new 16nm FinFET technology for digital and SoC applications, as well as 3D IC chip stacking technology by announcing the readiness of reference flows through our Open Innovation Platform® (OIP) collaboration.

The 16nm reference flow features FinFET-specific design solutions and methodologies for performance, power, and area optimization. The flow covers place-and-route, RC extraction, timing analysis, electromigration, IR-drop, and physical verification. In addition, it includes analysis capability for layout-dependent-effects (LDE) and voltage-dependent rule checking (VDRC) to improve custom design accuracy and productivity.

The 3D IC Reference Flow is an extension of our previously announced CoWoS™ Reference Flow that addresses true 3D chip stacking. The 3D IC flow provides a complete solution for through-silicon via (TSV) modeling, power integrity, thermal analysis, chip-package-board switching noise analysis, and design for test (DFT) for memory integration through a Wide IO interface. These tools allow customers to fully explore the new system integration opportunities made possible by 3D IC technology.

Intellectual Property

A strong portfolio of intellectual property rights strengthens TSMC’s technology leadership and protects our advanced and leading edge technologies. In 2013, TSMC received a record breaking 940 U.S. patents, as well as 500+ issued patents in Taiwan and the PRC, and other patents issued in various other countries. In 2013, TSMC ranked #35 in the “Top 50“ U.S. patent grants. TSMC’s patent portfolio now exceeds 20,000 patents worldwide (including patent applications in queue). We continue to implement a unified strategic plan for TSMC’s intellectual capital management. Strategic considerations and close alignment with the business objectives drive the timely creation, management and use of our intellectual property.

At TSMC, we have built a process to extract value from our intellectual property by aligning our intellectual property strategy with our R&D, operations, business objectives, marketing, and corporate development strategies. Intellectual property rights protect our freedom to operate, enhance our competitive position, and give us leverage to participate in many profit-generating activities.

We have worked continuously to improve the quality of our intellectual property portfolio and to reduce the costs of maintaining it. We plan to continue investing in our intellectual property portfolio and intellectual property management system to ensure that we protect our technology leadership and receive maximum business value from our intellectual property rights.

TSMC University Collaboration Programs

TSMC University Research Centers in Taiwan

TSMC has significantly expanded its interaction with universities in Taiwan with the establishment of several new research centers located at the nation’s most prestigious universities. The mission of these centers is twofold: to increase the number of highly qualified students who are suitable for employment at TSMC, and to inspire university professors to initiate research programs that focus on the frontiers of semiconductor device, process and materials technology; semiconductor manufacturing and engineering science; and specialty technologies of relevance to the semiconductor industry. Two of these research centers were established in 2013 at National Taiwan University and National Chiao Tung University, and two additional centers will be established at National Cheng Kung University and National Tsing Hua University in 2014. These centers are funded jointly by governmental agencies together with a commitment from TSMC of several hundred million Taiwan dollars and in-kind university shuttles. In 2013, about three hundred high caliber students across Electronics, Physics, Materials Engineering, Chemistry, Chemical Engineering and Mechanical Engineering disciplines joined the research centers.

TSMC University Shuttle Program

The TSMC University Shuttle Program was established to provide professors at leading research universities worldwide with access to the advanced silicon process technologies that are needed to research and develop innovative circuit design concepts. This program links motivated professors and graduate students with enthusiastic managers at TSMC with the goals of promoting excellence in the development of advanced silicon design technologies, and the nurturing of new generations of engineering talent in the semiconductor field.

The program provides access to silicon process technologies including the 65nm and 40nm nodes for digital, analog/mixed-signal circuits and RF design, and the 0.11μm/0.18μm process nodes for micro-electromechanical system designs. Select research projects utilize the 28nm technology node. Participants in the TSMC University Shuttle Program include major university research groups in the U.S.: M.I.T.; Stanford University; UC Berkeley; UCLA; University of Texas at Austin; and University of Michigan. In Taiwan, participants are: National Taiwan University; National Chiao Tung University; and National Tsing Hua University. Other participants include: Tsing Hua University in Beijing; The Hong Kong University of Science and Technology; and Singapore’s Nanyang Technological University.

TSMC’s University Shuttle Program participants recognize the importance of the program in allowing their graduate students to implement exciting designs ranging from: low-power memories; analog-to-digital converters; and advanced radio-frequency and mixed-signal bio-medical systems. This is truly a “win-win“ collaboration. In 2013, TSMC received specific letters of appreciation from professors at M.I.T., Stanford University, UC Berkeley, UCLA, University of Michigan, National Taiwan University and National Chiao Tung University.

Future R&D Plans

In light of the significant accomplishments of TSMC’s advanced technologies in 2013, the Company plans to continue to grow its R&D investments. The Company plans to reinforce its exploratory development work on new transistors and technologies, such as 3D structures, strained-layer CMOS, high mobility materials and novel 3D IC devices. These studies of the fundamental physics of nanometer CMOS transistors are core aspects of our efforts to improve the understanding and guide the design of transistors at advanced nodes. The findings of these studies are being applied to ensure our continued industry leadership at the 28nm and 20nm nodes and to extend our leadership to the 10nm and 7nm nodes. One of TSMC’s goals is to extend Moore’s Law through both innovative in-house work and by collaborating with industry leaders and academia. We seek to push the envelope in finding cost-effective technologies and manufacturing solutions.

TSMC intends to continue working closely with international consortia and lithography equipment suppliers to ensure the timely development of 193nm high-NA scanner technology, EUV lithography, and multiple- e-beam direct-write technologies. These technologies are increasingly important to TSMC’s process development efforts at the 10nm, 7nm, and smaller nodes.

Similarly, TSMC continues to work with mask writing, inspection, and repair equipment suppliers to develop viable mask-making technology to help ensure that the Company maintains its leadership position in mask quality and cycle time and continues to meet aggressive R&D, prototyping, and production requirements.

With a highly competent and dedicated R&D team and its unwavering commitment to innovation, TSMC is confident of its ability to deliver the best and most cost-effective SoC technologies for its customers, thereby supporting the Company’s business growth and profitability.

TSMC R&D Future Major Project Summary

Project Name

Description

Risk Production
(Estimated Target Schedule)

10nm logic platform technology and applications

3rd generation FinFET technology for both digital and analog products

2015

7nm logic platform technology and applications

CMOS platform technology for SoC

2017

3D IC

Cost-effective solution with better form factor and performance for SIP

2014 ~ 2016

Next-generation lithography

EUV and multiple e-beam to extend Moore’s Law

2014 ~ 2019

Long-term research

Special SoC technology (including new NVM, EMS, RF, analog) and 5nm transistors

2014 ~ 2019

The above plans accounted for roughly 70% of the total R&D budget in 2014. The total R&D budget is currently estimated to be around 8% of 2014 revenue.