Annual Reports  >  2014  >  Operational Highlights > Technology Leadership
Technology Leadership
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R&D Organization and Investment

In 2014 TSMC continued to invest in R&D with Total R&D expenditure amounting to 8% of revenue, a level that equals or exceeds the RD investment of many other high technology leaders.

Amount: NT$ thousands

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TSMC recognizes that the technology challenge required to extend Moore’s Law, the business law behind CMOS scaling, is becoming increasingly complex. The efforts of the R&D organization are focused on enabling the Company to continuously offer its customers first-to-market, leading-edge technologies and design solutions that contribute to their product success in today’s complex and challenging market environment. In 2014 the R&D organization met these challenges by introducing into manufacture the industry leading 16FF+ technology, the first integrated technology platform to make use of 3D FinFET transistors. The R&D organization continues to strengthen the pipeline of technology innovations that are required to maintain technology leadership. The 10nm technology advanced development continues with the goal of entering risk production in 2015, while the 7nm technology has now moved into the advanced development stage.

In addition to CMOS logic, TSMC conducts research and development on a wide range of other semiconductor technologies that provide the functionality our customers require for mobile SoC and other applications. Highlights achieved in 2014 include: introduction of our TSV platform, and expansion of the range of CoWoS® 3D packaging technology to the most advanced Si technologies; development of ultra-low power RF technologies in 28nm, 40nm and 55nm nodes aimed at meeting the demand for IoT (Internet-of-Things) applications; the introduction into manufacturing of MEMs process technologies for accelerator and microphone applications, and a 100V GaN power transistor technology.

TSMC maintains a network of important external R&D partnerships and alliances with world-class research institutions, such as IMEC, the respected European R&D consortium, where TSMC is a core partner. TSMC also provides funding for nanotechnology research at leading universities worldwide to promote innovation and the advancement of nano-electronic technology. In 2014 TSMC announced the formation of joint research centers at National Tsing Hua University and National Cheng Kung University, with the aim of developing greater understanding into the devices and materials used in the manufacture of advanced Si technologies.

R&D Accomplishments in 2014

R&D Highlights

  • 20nm Technology

TSMC’s 20nm technology was successfully qualified for volume manufacture and currently in mass production.

  • 16nm Technology

16FF+ technology passed full reliability qualification in the fourth quarter of 2014. This technology features FinFET transistors with a third generation High-k/Metal Gate process, a fifth generation of transistor strain process, and advanced 193nm lithography. This enhanced version of TSMC’s 16FF technology operates 40% faster than planar 20nm System-on-Chip technology (20SoC) or consumes 50% less power at the same speed. More than 15 customers and IP vendors have verified their IP with the 16FF+ technology.

  • 10nm Technology

10nm technology will offer substantial power reduction for the same chip performance compared to earlier technology generations. Development activities in 2014 focused on manufacturing baseline process setup, yield learning, transistor performance improvement, and reliability evaluation. TSMC plans to enter 10nm risk production in 2015 and volume production in 2016.

  • 7nm Technology

2014 saw the introduction of 7nm technology into advanced development. The 7nm technology will offer substantial density improvement and power reduction for the same chip performance compared to 10nm technology. Development activities in 2015 will focus on selection of transistor architecture, baseline manufacturing process setup for both transistors and interconnects, and initial reliability evaluations. TSMC plans to enter 7nm full development in 2016 for risk production in 2018.

  • Lithography

The focus of TSMC’s R&D efforts in lithography is 10nm development. This technology requires special resolution enhancement techniques to enable immersion tools to image geometries beyond 16nm. Coupling these enhancements with advanced patterning that was developed for the 20nm and 16nm nodes allows the immersion technique to meet 10nm requirements.

In 2014, TSMC received delivery of a second NXE3300 extreme ultraviolet (EUV) scanner. The associated process and equipment R&D is on-going. TSMC has been working with ASML to raise its capabilities to meet the requirements of the 7nm technology node. Looking beyond 7nm, multiple e-beam direct-write lithography (MEB DW) is being investigated as a lithography solution.

  • Mask Technology

Mask technology is an integral part of our advanced lithography. Having completed the transfer of mask technology for the 16nm node to the mask production organization in 2014, R&D made substantial progress on developing mask technology for the 10nm node. The R&D team also made solid progress in the mask technology for EUV lithography, continuing to work with suppliers and consortia in developing the required infrastructure.

Integrated Interconnect and Packaging

  • 3D IC

TSMC qualified for manufacture a new TSV-based platform in 2014. This is an important industrial milestone to integrate TSV with active devices. The CoWoS® technology continues to expand its application from FPGA to network and to high performance computing. The choice of top dies on CoWoS® technology is also expanding quickly from 65/40nm to the most advanced 20nm and 16nm FinFET technology. In parallel with TSV-based platforms above, InFO, or integrated fan out, is being developed as a non-TSV technology for cost-sensitive applications such as mobile and consumer products. It is expected to become the most important backend technology for TSMC in the next few years. An ultra-thin, fine pitch InFO_PoP packaging technology has been successfully demonstrated with outstanding characteristics and qualified for manufacture.

  • Advanced Package Development

TSMC offers a wide variety of lead-free packaging technologies for mobile/handheld devices and applications. In 2014, TSMC qualified 16nm FinFET Si with ultra-fine pitch copper (Cu) bump BoT (Bump-on-Trace) packaging technology, and the innovative Fan-in WLP technology (UBM-Free Fan-in WLP) with excellent reliability performance.

  • Advanced Interconnect

Development of low resistance Cu and low capacitance dielectric continued to be the primary focus in 2014. At the 10nm node, a new patterning process and a novel dielectric scheme have been developed to shrink line width/space and reduce the capacitance between copper lines. For the 7nm node and beyond, TSMC has developed a new advanced patterning scheme that allows copper line width and spacing to be further reduced. A low resistivity metal scheme was developed. The circuit delay of copper lines developed with these advanced processes is highly competitive and is lower than that projected by the International Technology Roadmap for Semiconductors (ITRS).

Advanced Transistor Research

Enhancing the speed and lowering the power requirements of advanced logic technologies requires innovation in transistor architectures and materials. TSMC is at the forefront of research in these areas with a focus on high mobility channel materials, such as germanium and III-V compound semiconductors. Record-breaking germanium transistor performance was recently achieved and reported at the 2014 IEDM.

Specialty Technologies

TSMC offers a broad mix of technologies to address the wide range of applications.

  • Mixed Signal/Radio Frequency (MS/RF) Technology

TSMC has started to develop ultra-low power RF technologies in 28nm, 40nm and 55nm nodes aimed at the expected strong demand in low power and low cost IoT (Internet-of-Things) applications, and began development of a 0.18μm SOI process to replace traditional compound semiconductor-based solutions in cellar/wi-fi RF switch applications.

  • Power IC/BCD Technology/Panel Drivers

The second generation of 0.18µm BCD technology has been extended to offer lower cost and higher performance devices, enabling more integration in mobile power ICs.

  • Micro-electromechanical Systems (MEMS) Technology

In 2014, TSMC’s modular MEMS technology was qualified for manufacture of accelerometers and high-resolution noise cancellation microphones. Future plans include development of next generation products, and BioMEMS applications.

  • GaN Technology

TSMC is the first foundry to implement GaN technology in a 6-inch fab. The R&D team completed development and qualified for manufacture a high electron mobility transistor (100V E-HEMT) configuration for high power, high frequency applications with low Ron resistance and high breakdown voltage.

  • Flash/Embedded Flash Technology

TSMC achieved several important milestones in embedded flash technologies. At the more mature 65nm/55nm node, NOR-based cell technologies, including 1-T cell and Split-Gate cell, successfully completed customer qualification. At the 40nm node, the split-gate cell technology was shipped for both automotive and consumer applications. Embedded flash development for the 28LP and 28HPM platforms is underway for such low leakage applications as smartcard, MCU and Automobile.

Technology Platform

TSMC provides customers with advanced technology platforms that include the comprehensive design infrastructure required to optimize design productivity and cycle time. These include: design flows for electronic design automation (EDA); silicon-proven IP building blocks, such as libraries; and simulation and verification design kits, i.e., process design kits (PDK) and technology files.

The availability of 16FF+ saw improvements in design infrastructure using an advanced CPU core as the vehicle to support customers’ adoption of 16nm FinFET Plus (EDA tool certification results can be found on TSMC-Online). TSMC also extended its IP quality program (TSMC9000) to allow IP audits to be performed either at TSMC or at TSMC-certified laboratories. To help customers plan new product tape-outs incorporating IP/Library from TSMC Open Innovation Platform® (OIP) ecosystem, the OIP ecosystem now features a portal to connect customers to an ecosystem of 39 solution providers.

Design Enablement

TSMC’s technology platforms provide a solid foundation for design enablement. Customers can design directly using the Company’s internally developed IP and tools, or using those that are available via our OIP partners.

Tech File and PDK

TSMC provides a broad range of process design kits (PDK) for digital logic, mixed-signal, radio frequency (RF), high-voltage driver, CMOS Image Sensor (CIS) and embedded flash technologies across a range of technology nodes from 0.5µm to 16nm. In addition, TSMC provides technology files for: DRC, LVS, RC extraction, automatic place and route, and a layout editor to ensure process technology information is accurately represented in EDA tools. By 2014, TSMC has provided more than 7,000 technology files and more than 150 PDKs in TSMC-Online. There are more than 100,000 customer downloads of these files every year.

Library and IP

TSMC and its alliance partners offer our customers a rich portfolio of reusable IP, which are essential building blocks for many circuit designs. In 2014, over 60% of new tape-outs at TSMC adopted one or more libraries or IP from TSMC and/ or our IP partners. In 2014, TSMC expanded its library and silicon IP portfolio to contain more than 8,500 items, a 28% increase over 2013.

Design Methodology and Flow

In 2014 TSMC addressed the critical design challenges associated with the new 16nm FinFET Plus technology for digital and SoC applications by announcing the readiness of reference flows through OIP collaboration that feature FinFET-specific design solutions and methodologies for performance, power and area optimization.

Intellectual Property

A strong portfolio of intellectual property rights strengthens TSMC’s technology leadership and protects our advanced and leading edge technologies. In 2014, TSMC received a record breaking 1460 U.S. patents, as well as 450+ issued patents in Taiwan and the PRC, and other patents issued in various other countries. In 2014, TSMC ranked #23 in the “Top 50” U.S. patent grants. TSMC’s patent portfolio now reaches almost 30,000 patents worldwide (including patent applications in queue). We continue to implement a unified strategic plan for TSMC’s intellectual capital management. Strategic considerations and close alignment with the business objectives drive the timely creation, management and use of our intellectual property.

At TSMC, we have built a process to extract value from our intellectual property by aligning our intellectual property strategy with our R&D, operations, business objectives, marketing, and corporate development strategies. Intellectual property rights protect our freedom to operate, enhance our competitive position, and give us leverage to participate in many profit-generating activities.

We have worked continuously to improve the quality of our intellectual property portfolio and to reduce the costs of maintaining it. We plan to continue investing in our intellectual property portfolio and intellectual property management system to ensure that we protect our technology leadership and receive maximum business value from our intellectual property rights.

TSMC University Collaboration Programs

TSMC University Research Centers in Taiwan

TSMC has significantly expanded its interaction with universities in Taiwan with the establishment of four research centers located at the nation’s most prestigious universities. The mission of these centers is twofold: to increase the number of highly qualified students who are suitable for employment in semiconductor industry, and to inspire university professors to initiate research programs that focus on the frontiers of semiconductor device, process and materials technology; semiconductor manufacturing and engineering science; and specialty technologies for electronic applications. Following the establishment of two research centers at National Taiwan University and National Chiao Tung University in 2013, two additional centers were set up at National Cheng Kung University and National Tsing Hua University in 2014. These centers are funded jointly by governmental agencies together with a commitment from TSMC of several hundred million Taiwan dollars and in-kind university shuttles. In 2014, several hundred high caliber students across Electronics, Physics, Materials Engineering, Chemistry, Chemical Engineering and Mechanical Engineering disciplines joined the research centers.

TSMC University Shuttle Program

The TSMC University Shuttle Program was established to provide professors at leading research universities worldwide with access to the advanced silicon process technologies needed to research and develop innovative circuit design concepts. This program links motivated professors and graduate students with enthusiastic managers at TSMC with the goals of promoting excellence in the development of advanced silicon design technologies, and the nurturing of new generations of engineering talent in the semiconductor field.

The program provides access to such silicon process technologies as 65nm and 40nm nodes for digital, analog/ mixed-signal circuits and RF design, and the 0.11μm/0.18μm process nodes for micro-electromechanical system designs. Select research projects utilize the 28nm technology node. Participants in the TSMC University Shuttle Program include major university research groups in the U.S.: M.I.T., Stanford University, UC Berkeley, UCLA, University of Texas at Austin, and University of Michigan. In Taiwan, participants are: National Taiwan University, National Chiao Tung University, and National Tsing Hua University. Other participants include: Tsing Hua University in Beijing, The Hong Kong University of Science and Technology, and Singapore’s Nanyang Technological University.

TSMC’s University Shuttle Program participants recognize the importance of the program in allowing their graduate students to implement exciting designs such as low-power memories, analog-to-digital converters, and advanced radio-frequency and mixed-signal bio-medical systems. This is truly a “win-win” collaboration. In 2014, TSMC received specific letters of appreciation from professors at M.I.T., Stanford University, UC Berkeley, UCLA, University of Michigan, National Taiwan University and National Chiao Tung University.

Future R&D Plans

In light of the significant accomplishments of TSMC’s advanced technologies in 2014, the Company plans to continue to grow its R&D investments. The Company plans to reinforce its exploratory development work on new transistors and technologies, such as 3D structures, strained-layer CMOS, high mobility materials and novel 3D IC devices. These studies of the fundamental physics of nanometer CMOS transistors are core aspects of our efforts to improve the understanding and guide the design of transistors at advanced nodes. The findings of these studies are being applied to ensure our continued industry leadership at the 20nm and 16nm nodes and to extend our leadership to the 10nm and 7nm nodes. One of TSMC’s goals is to extend Moore’s Law through both innovative in-house work and by collaborating with industry leaders and academia. We seek to push the envelope in finding cost-effective technologies and manufacturing solutions.

With a highly competent and dedicated R&D team and its unwavering commitment to innovation, TSMC is confident of its ability to deliver the best and most cost-effective SoC technologies for its customers, thereby supporting the Company’s business growth and profitability.

TSMC R&D Future Major Project Summary

Project Name

Description

Risk Production
(Estimated Target Schedule)
10nm logic platform technology and applications 3rd generation FinFET technology for both digital and analog products

2015

7nm logic platform technology and applications CMOS platform technology for SoC

2018

3D IC

Cost-effective solution with better form factor and performance for SiP

2015 ~ 2016

Next-generation lithography EUV and multiple e-beam to extend Moore’s Law

2015 ~ 2019

Long-term research

Special SoC technology (including new NVM, MEMS, RF, analog) and 5nm transistors

2015 ~ 2019

The above plans accounted for roughly 70% of the total R&D budget in 2015. The total R&D budget is currently estimated to be around 8% of 2015 revenue.