With the evolution from planar to 3D FinFET transistor structures for key smartphone and high performance computing applications, thermal sensing becomes a critical issue. Chip designers need to optimize their products around thermal hotspots to optimize for both performance and longevity.
This paper analyzes device-structure-induced and process- dependent temperature inaccuracy sources of thermal sensing applications in FinFETs: Self-heating and Joule-heating interaction, non-uniform FinFETarray temperature distribution, and distance limitation due to gate-area non-uniformity. Thermal behaviors of these inaccuracy sources are comprehensively characterized to mitigate the temperature gap between hot-spots and measurements.
STT-MRAM or Spin-Torque-Transfer Magnetic Random Access Memory is an emerging memory type that offers lower cost and improved performance over embedded Flash used in older generation logic technologies to provide non-volatile memory capability. As logic density continues to increase, it becomes prohibitively expensive to continue to embed Flash memory with it. In this paper, TSMC describes a STT-MRAM embedded in our 22nm ultra low-leakage process.
TSMC has developed this technology to be robust with high yield and reliability along with a wide operating temperature range and high magnetic field immunity, ideal for demanding applications like automotive.
Extending Moore's Law necessarily means that TSMC needs to raid the periodic table for new elements and materials. One of the early candidates for a new material is good old carbon. Carbon can exist in many forms or allotropes including graphite, diamonds, graphene or Carbon Nanotubes (CNT). Semiconducting CNTs may offer the potential to augment silicon based transistors by offering key properties such as excellent heat conductivity as well as high electrical mobility as well as Backend-of-Line (BEOL) compatible processability.
TSMC demonstrates the first integration of Carbon Nanotubes with an advanced production level silicon based transistors. A necessary first step in the investigation of any new material and its processes.
5G and mmWave bring into focus the need for new and optimized antenna designs. Millimeter wave systems are particularly susceptible to structure discontinuity and impedance mismatch. These potential limits to mmWave performance are often created in the chip-package-board interface for both antenna on PCB and antenna in substrate applications.
TSMC extends our Advanced Packaging technologies to create 3D dipole antennas by harnessing our wafer level integrated fan-out (InFO) packaging process. We can create 3D dipole antenna structures that are thicker than 100μm using redistribution layer metals (RDL), resulting in 25% bandwidth and 6dB gains. Integrated with our 40nm CMOS front-end RF circuits, we can demonstrate the antenna arrays' functionality and beam-forming capabilities.
Artificial Intelligence both Machine Learning and Inferencing as well as High Performance Computing are continuing to push the boundaries of what is possible in compute. AI and HPC applications seemingly have an insatiable appetite for more computing capacity and memory bandwidth and power to feed these systems. In addition to silicon-based innovations, TSMC has lead the world with our Advanced Packaging technologies to enable the visions of our AI and HPC customers.
TSMC has continued to innovate on our Chip-on-Wafer-on-Substrate packaging. Our latest innovations include integrating High-K based deep trench capacitors for the first time with our silicon interposers through Silicon VIAs and fine-pitch interconnects. This technology allows low-cost, large footprint packages ideal for multiple die / memory combinations for AI and HPC products.
The proliferation of AI and the deployment of 5G networks accelerate the transformation of our society into a highly connected world. Semiconductors are the indispensable elements in realizing all the product innovations. The progress and challenges of the state of art CMOS technology and advanced packaging will be reviewed.
Industry-leading 5nm CMOS technology features, for the first time, full-fledged EUV, and high mobility channel finFETs with densest 0.021μm2 SRAM offering ~1.84x logic density, 15% speed gain or 30% power reduction over previous generation. This true 5nm technology successfully passed qualification with high yield, and is on track for high volume production in 1H 2020.