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Home > TSMC 2017 Open Innovation Platform® Ecosystem Forum Technical Papers > Maximizing ROI for 7nm SoCs with Synopsys' Convergent Digital Design Platform (Synopsys)
Maximizing ROI for 7nm SoCs with Synopsys' Convergent Digital Design Platform (Synopsys)    
Live EDA Technical Presentations
HiSilicon Achieves PPA Targets Quicker Using PrimeTime POCV to Reduce Design Margin on TSMC N7 FinFET process (Synopsys / HiSilicon)
Advanced Process Node Server Processor Design: Successful Implementation of Enhanced Calibre SmartFill Methodology (Mentor, a Siemens Business / Qualcomm)
Generating DRC and Electrically Correct Placed-and-Routed Arrays Using the TSMC 7nm Process (Cadence Design Systems)
Improving Physical Verfication Performance and Productivity for Latest GPU Designs (Synopsys / NVIDIA)
Clock KPI System for Better PPA of Complex Clock Design with ClockExplorer (Huada Empyrean Software / Spreadtrum Communications)
Maximizing ROI for 7nm SoCs with Synopsys' Convergent Digital Design Platform (Synopsys)
Achieving optimal PPA for Cortex-A75 ARMR Processors using TSMC FinFET Technology with Cadence Digital Tools (Cadence Design Systems / Arm)
Mixed-signal Parasitic Flow using TSMC N16 and Mentor Calibre xACT Solution (Mentor, a Siemens Business / eTopus Technology)
Utilizing Circuit Simulator API to Perform Complex Custom Analysis in Advanced Process Node (Oracle / Silvaco)
System Planning for CoWoS and InFO Technologies (Cadence Design Systems)
Stacked Device Enablement for Advanced Analog Design Simulations (Synopsys / Xilinx)
An EM-aware methodology for a high-speed multi-protocol 28Gbps SerDes design with TSMC 16FFC (Helic / Wipro / NXP)
Using Pegasus™ Verification System for Advanced Node Design rule Check (DRC) (Cadence Design Systems / Microsemi)
10nm/7nm Demand an Innovative Approach to SRAM IP Verification for Improved Manufacturability (Mentor, a Siemens Business / MediaTek)
Live IP Technical Presentations
Live Design Service Technical Presentations
Print-Only Technical Presentations
 
Abstract:

Scaling to lower geometries is constrained not only by metallurgy and lithography challenges, but also by the need for an evolution in physical design methodologies to extract the maximum ROI at the 7-nm process node. With the advent of cell height reduction for pitch scaling, heterogeneous stack-driven RC management, and the ever-increasing impact of waveform distortion as well as non-Gaussian effects, this node demands a flow-wide reassessment for best ROI. In this talk, Synopsys' senior R&D member will describe how several key innovations in IC Compiler II, along with a distinctively architected integration flow with Design Compiler, StarRC and PrimeTime, offers the most compelling solution for designers to realize their 7-nm entitlement. Data will be presented to show that this flow is reducing design-in-margins, while offering higher utilization rates, best QoR and the fastest path to design closure.




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