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Home > TSMC 2017 Open Innovation Platform® Ecosystem Forum: Technical Papers
TSMC 2017 Open Innovation Platform Ecosystem Forum
Technical Papers
   
The TSMC OIP Ecosystem Forum brings together TSMC's design ecosystem companies and our customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event.

More than 90% of last year's attendees said that, "the forum helped me better understand TSMC's Open Innovation Platform" and that "I found it effective to hear directly from TSMC OIP member companies."

This year's event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies to address your design challenges!

This year, the forum is a day-long conference kicking-off with trend-setting keynotes and announcements from TSMC and leading IC design company executives.

The technical sessions are dedicated to 33 selected technical papers from TSMC's EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 60 member companies showcasing their products and services.
Fourteen Live EDA Technical Presentations
HiSilicon Achieves PPA Targets Quicker Using PrimeTime POCV to Reduce Design Margin on TSMC N7 FinFET process (Synopsys / HiSilicon)
Advanced Process Node Server Processor Design: Successful Implementation of Enhanced Calibre SmartFill Methodology (Mentor, a Siemens Business / Qualcomm)
Generating DRC and Electrically Correct Placed-and-Routed Arrays Using the TSMC 7nm Process (Cadence Design Systems)
Improving Physical Verfication Performance and Productivity for Latest GPU Designs (Synopsys / NVIDIA)
Clock KPI System for Better PPA of Complex Clock Design with ClockExplorer (Huada Empyrean Software / Spreadtrum Communications)
Maximizing ROI for 7nm SoCs with Synopsys' Convergent Digital Design Platform (Synopsys)
Achieving optimal PPA for Cortex-A75 ARMR Processors using TSMC FinFET Technology with Cadence Digital Tools (Cadence Design Systems / Arm)
Mixed-signal Parasitic Flow using TSMC N16 and Mentor Calibre xACT Solution (Mentor, a Siemens Business / eTopus Technology)
Utilizing Circuit Simulator API to Perform Complex Custom Analysis in Advanced Process Node (Oracle / Silvaco)
System Planning for CoWoS and InFO Technologies (Cadence Design Systems)
Stacked Device Enablement for Advanced Analog Design Simulations (Synopsys / Xilinx)
An EM-aware methodology for a high-speed multi-protocol 28Gbps SerDes design with TSMC 16FFC (Helic / Wipro / NXP)
Using Pegasus™ Verification System for Advanced Node Design rule Check (DRC) (Cadence Design Systems / Microsemi)
10nm/7nm Demand an Innovative Approach to SRAM IP Verification for Improved Manufacturability (Mentor, a Siemens Business / MediaTek)


Sixteen Live IP Technical Presentations
25-56Gbps Silicon Photonics on 28nm CMOS (Sofics)
High performance memory IP and sub-system for automotive applications (Cadence Design Systems)
New Hardware Security Solution Roll Out: the Highest Secure OTP solution and Multi-Dimensional Root of Trusts delivery to SoC chips (eMemory)
Cortex-A55 POP IP on 16FFC: Is Performance still King? (Arm)
High speed interconnect IPs for High Performance Computing and Enterprise Applications (Cadence Design Systems)
Circuit Design and Verification of 7nm Low-Power Low-Jitter PLL for HSC, Automotive, and IoT (Silicon Creations / Mentor, a Siemens Business)
Foundation IP for High-Performance Computing Designs on TSMC N7 FinFET Process (Synopsys)
Accelerating Development of Automotive ADAS SoCs with Certified IP (Synopsys)
Taking Advantage of 16FFC Process in MIPI PHY Design (M31 Technology)
Robust NVM Solutions for TSMC Specialty and Advanced FinFET Technologies (Sidense)
Taking Back the Power: Power Design Techniques for your Next SoC (Arm)
SoC Fabric IPs to Enable DVFS (Dolphin Integration)
Overcoming Timing Closure Issues in Wide Interface DDR, HBM and ONFI Subsystems (True Circuits)
Automotive OTP NVM in TSMC Advanced Process Nodes (Kilopass Technology)
Integration & Validation of eFPGA for Physical Designers (Flex Logix)
High Reliability IP for Automotive and Datacenter Applications (Analog Bits)


Three Live Design Service Technical Presentations
Advanced Solution for HPC Era (GUC)
High Bandwidth Memory (HBM2) IP Subsystem Silicon Validation and Interoperability with HBM2 Memory Die Stack (Open-Silicon)
The power of the network effect on TSMC's VCA ecosystem – An imec perspective (imec)


Five Print-Only Technical Presentations
Parasitic Challenges and Solutions with the Quantus QRC Extraction Solution for 7nm FinFET Designs (Cadence Design Systems)
Rule-based Clock Analysis for Lower Power and Higher Yield at Advanced Process Nodes (Huada Empyrean Software / HiSilicon)
Meeting ADAS SoC Safety Design Challenges with Active Safety Feature-Enabled IP (Cadence Design Systems)
Storage IP for Automotive Applications, a Bottleneck Relief (Cadence Design Systems)
Secure Supply Chain Enablement using JTAG IEEE 1149.1™| ECID and Non-Volatile Memory (Sidense)



"To view complete version of the presentations, please go to TSMC Online.
If you are already a TSMC customer or partner and would like to set up a new individual TSMC-Online account, please contact your internal TSMC-Online super user, or your account manager."

 
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