Philips, STMicroelectronics and TSMC Take Lead in Advanced 90-nanometer CMOS Process Technologies

Eindhoven, The Netherlands, Geneva, Switzerland and Hsin-Chu, Taiwan, March 5, 2002 – Royal Philips Electronics (NYSE: PHG, AEX: PHI), STMicroelectronics (NYSE: STM) and Taiwan Semiconductor Manufacturing Company Ltd. (TAIEX: 2330, NYSE: TSM) (“TSMC”) today announced that the three companies have reached agreement on a new advanced 90-nm (0.09-micron) CMOS process. The agreement between the three companies also includes the development of CMOS processes to the next technology node at 65-nm and beyond.

Test devices for 90-nm have already been successfully fabricated by ST and Philips in Crolles, France, and by TSMC in Hsin-Chu, Taiwan. Prototyping of 90-nm products is expected to take place in the second half of 2002. This development was made possible by leveraging the technical expertise of all three companies’ internal research and development teams and customer engineering organizations. The 90-nm process involves the collaborative resources of all three partners and their associated advanced laboratories, including Philips Research, IMEC, CEA/LETI and France Telecom R&D. The joint development agreement between Philips, ST and TSMC is expected to provide designers with early access to industry-leading 90-nm technology that is quickly transferable to high-volume production by all three companies. Customers that take advantage of this effort will further benefit by leading their markets – or creating new markets –with high-performance devices capable of supporting new and unique applications.

This joint project extends existing alliances among the three companies. STMicroelectronics and Philips’ semiconductors division have been cooperating since 1992 on joint development of CMOS digital and mixed-signal processes, a cooperation that was strengthened and extended in 2000. Similarly, Philips and TSMC have collaborated in process research and development since the founding of TSMC in 1987. This landmark collaboration, which brings TSMC together with two of the world’s largest producers of semiconductors, allows the three companies to reinforce their R&D efforts in leading edge technology.

The technology developed by the three partners has already been validated on fully functional test chips produced on the ST/Philips pilot line in Crolles, France and at TSMC Fab3’s R&D facilities in the fourth quarter of 2001. These test chips included 1-Mbit and 4-Mbit of embedded static RAM (SRAM). The SRAM density of 735kbit/mm2, already one of the highest in the world, will be further increased by the end of the year when the SRAM cell size is reduced from its initial 1.36μm2 to 1.27μm2.

“The development of this process will give our customers early access to an advanced System-on-Chip process that supports high performance processors and peripherals, together with embedded DRAM and SRAM and enables us to exploit the scalability of our Nexperia architectures to even greater complexities within the shortest time to market,” said Theo Claasen, Chief Technology Officer at Philips Semiconductors. “Leveraging the expertise of the three companies, we will be in a leading position to offer the world’s most advanced and manufacturing-efficient CMOS technology. A rich library of standard cells is already available, and the strong partnership between the three industry-leading members is expected to stimulate IP providers to generate even more offerings.”

“ST has already proven its ability to design and manufacture advanced complex System-on-Chip solutions for its world-leading customers and is now moving forward to the next level of advanced process technology. This joint development project is not simply an alignment of design rules. Thanks to our initial collaboration on fundamental technical issues and the ongoing interchange of data, we can be sure that the processes of all three partners in