Hsinchu, Taiwan, April 6, 2001 --Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE: TSM), the world’s largest dedicated semiconductor foundry, today announced the availability of the industry’s first “manufacturability focused” IC design Reference Flow, providing designers with a silicon-proven methodology that dramatically reduces time-to-volume by enabling direct manufacturability to the world’s leading foundry processes.
The first generation of Reference Flow is silicon-proven in TSMC’s 0.25-micron and 0.18-micron technologies, and is available immediately. The company is already in development with the next generation Reference Flow, which targets TSMC’s leading-edge 0.15- and 0.13-micron technologies.
To achieve the shortest design cycle times and the best possible manufacturability, the TSMC Reference Flow features a physical synthesis-based, timing-driven implementation flow for efficient timing closure. In addition, the flow includes extensive RC and delay correlation from real silicon throughout the design flow. Special features address critical signal integrity issues, such as IR drop and crosstalk, in deep-submicron designs. Guidelines for “metal slotting” and “dummy metal” layering – techniques to minimize stress and improve reliability and process margins – are also included.
“This TSMC Reference Flow is a critical development for designers who need a quick, easy way to get from concept to silicon,” said Dr. Ping Yang, vice president of design services for TSMC. “Most important, the Reference Flow dramatically improves design-for-manufacturability to companies who need fast time-to-volume.”
“Oak Technology has been using the Reference Flow as an early adopter since August 2000 as our design flow and methodology,” said Darmin Jin, Senior Design Manager at Oak Technology. “The reference flow saves time and effort that would otherwise be spent building the design flow from scratch. In addition, its quality is exceptionally high.
“For example, the Reference Flow helped us to detect antenna violations that would have been missed by our original flow,” continued Mr. Jin. “We can use the flow to achieve more efficient timing closure. Based on real-world experience, we benefit from the Reference Flow by shortening our design cycle, and gaining confidence in our tape-out.”
“TSMC leads the foundry industry in providing advanced design services to our customers, including the industry’s largest library offering and the most advanced IP catalog, In addition, we lead the industry in providing technology files collaboratively with best-of-class EDA vendors,” said Mike Pawlik, vice president of corporate marketing for TSMC. “The development of this industry-first Reference Flow ties all of these elements together by providing customers with a silicon-proven design methodology that addresses advanced design challenges, enabling dramatically faster time-to-market for our customers.”
Design tools in the Reference Flow were developed by EDA Alliance partners who have worked closely with TSMC for many years to identify and resolve design-to-process issues. EDA Alliance partners who have collaborated extensively with TSMC include Synopsys, Inc., and Avanti Corp. Other EDA companies may be included in this flow as new generations of the flow are released.
“Synopsys clearly recognizes the benefit of a silicon-proven Reference Flow for the design community, and has committed engineering resources to develop and support the flow,” said Deirdre Hanford, senior vice president, Business and Market Development at Synopsys. “By working together on design methodologies for simulation, formal and static verification, test, and physical synthesis, Synopsys and TSMC are addressing the increasingly