MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Aug. 15, 2000--Synopsys, Inc. (Nasdaq:SNPS) and Taiwan Semiconductor Manufacturing Corporation (TSMC) (NYSE:TSM), today announced an agreement to jointly develop silicon-calibrated technology files across TSMC's advanced processes, including 0.13-micron, for Synopsys' Arcadia(R) layout parasitic extraction tool. The result of this partnership provides joint customers with a higher level of confidence to design high-quality integrated circuits (ICs) and enables first-pass silicon success. Arcadia technology files for the popular TSMC processes have been certified and are available for download from TSMC's password-controlled website.
"TSMC is focused on delivering the industry's most advanced process technology to our customers to ensure high performance and reliability resulting in first-pass silicon success," said Mike Pawlik, vice president of corporate marketing for TSMC. "Collaborating with a leader like Synopsys, and delivering the fruits of the partnership quickly via the Internet, will help to shorten our customers' development time and allow them to quickly ramp up their production of complex chips."
"Arcadia's accurate parasitic extraction is the foundation for effective power, timing and reliability analysis," said Dr. Antun Domic, vice president and general manager of Synopsys' Nanometer Analysis and Test Group. "By partnering with TSMC early in the development of TSMC's most advanced processes, Synopsys can deliver certified Arcadia technology files to our mutual customers immediately upon the availability of TSMC's process technology. Together, we help our customers realize the full potential of silicon performance, and shorten their design cycles."
Under this agreement, Synopsys and TSMC will jointly develop test chips and silicon-calibrated Arcadia technology files. Using the Arcadia technology files, fabless IC designers can realize unprecedented accuracy with Synopsys tools when they target TSMC fabs, allowing the TSMC customers to gain full-chip verification prior to committing to final design tape-out.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading manufacturing capacity, process technology, library and IP options and other leading-edge foundry services. TSMC is constructing or operating 11 fabs and has substantial capacity commitments at three additional facilities jointly operated by TSMC and its partners. In 2000, TSMC expects to have the capacity for nearly 3.4 million 8-inch equivalent wafers, increasing to 4.7 million wafers in 2001. In addition, TSMC recently became the first foundry to license its technology to a leading IDM, thereby establishing itself as an acknowledged world leader in process technology. Fabrication processes offered by TSMC include CMOS logic, mixed-mode, volatile and non-volatile memory, and BiCMOS. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. More information about TSMC is available through the World Wide Web at http://www.tsmc.com.
Arcadia is a full chip and net-by-net RC extraction solution used by IC designers for custom, DSP, memory and high-end ASIC designs. Arcadia's high accuracy, user-friendliness and seamless integration with Synopsys timing, power and reliability flows enable improved chip performance and reduced time-to-market.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit