MOSYS And TSMC Partner TO Expand Range Of 1T-SRAM? High Density Memory TechnologiesNew SoC memory technology options provide greater density, lower standby power

SUNNYVALE, CA and SAN JOSE, CA, (April 9, 2001) - MoSys, Inc. and Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM) announced today that the two companies have struck a far-reaching agreement that sets new memory density and power benchmarks for the foundry industry. The extensive agreement includes two initiatives, one providing for the delivery of two new high-density embedded memory technologies in TSMC's most advanced silicon, and the other providing customized macro design services for designers using these memory technologies in system-on-chip (SoC) designs.

In satisfying the first initiative, TSMC and MoSys have co-developed an expanded range of very-high-density 1T-SRAM memory options with two new high-density memory technologies supporting TSMC's advanced 0.13-micron logic process. These new memory technologies are 1T-SRAM-M?, for very low power applications, and 1T-SRAM- X?, which doubles memory density compared to standard 1T-SRAM without compromising speed or power.

The second initiative includes a 1T-SRAM technology licensing agreement calling for TSMC and MoSys to jointly offer customized memory macro design services to designers. TSMC has thus expanded its in-house IP design portfolio with the 1T-SRAM product, in addition to TSMC's standard SRAM and patented FlashIP.

"Embedded memory has the greatest impact on the cost structure of today’s chips," said Mike Pawlik, vice president of corporate marketing for TSMC. "TSMC is offering these unique memory technologies to help designers reach higher levels of integration and create even more cost-effective high-performance products, without impacting the characteristics of the logic and analog portions of their designs."

The 1T-SRAM-M will offer high performance together with very low power consumption for mobile, battery-powered applications, reducing standby power significantly compared with six-transistor SRAM on the same process, while maintaining the dramatic density advantages of 1T-SRAM. By utilizing an optimized TSMC logic process variant, 1T-SRAM-X will offer a further doubling of the memory density compared to standard 1T-SRAM without compromising the speed and power advantages of that technology, making it an excellent choice for those applicationsthat will require even larger amounts of high performance embedded memory.

"TSMC customers will benefit from the wider selection of 1T-SRAM, 1T-SRAM-M and 1T-SRAM-X solutions that provide the most cost effective high densityembedded memory building blocks tailored for a wide range of application requirements," said Dr. Fu-Chieh Hsu, president and CEO of MoSys. "The benefits extend far beyond improving customer products to enabling entirely new applications."

The 1T-SRAM technology will be a major focus at TSMC’s Technology Symposiums, which will be held on April 23rd in San Jose, Calif.; April 25th in Austin, Tex.; April 27th in Boston, Mass.; and April 30th in Costa Mesa, Calif. To register for any Symposium, go to and click on the Technology Symposium registration button.


The 1T-SRAM technology is available today for TSMC's 0.25-micron, 0.18-micron, and 0.15-micron standard logic processes. The new 1T-SRAM-M technology in the TSMC 0.13-micron geometry will be available in Q3 2001. Designers will be able to incorporate 1T-SRAM-X technology in to products based on TSMC's 0.13-micron geometry in Q4, 2001. Designers can order the technology by using the -M and -X designators following TSMC process nomenclature, e.g., CL013G-M and CL013G-X.


MoSys' patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other memory technologies. The single transistor bit cell used in 1T-SRAM technology results in the technolog