SAN JOSE, Calif., March 20, 2001 -- Taiwan Semiconductor Manufacturing Company (NYSE: TSM), the world’s largest dedicated semiconductor foundry, said today it is the first integrated circuit (IC) foundry to release silicon substrate data to selected electronic design automation (EDA) companies with expertise in substrate noise analysis. The new initiative shares critical mixed-signal process data for TSMC’s industry-leading 0.18-micron and 0.25-micron mixed-signal processes with Cadence Design Systems, Inc. and Simplex Solutions, Inc. Designers can use this improved analysis capability on system-on-chip (SOC) designs targeting TSMC’s mixed-signal processes.
These TSMC processes are the foundation for a variety of end-use products, including DSL modems, ethernet devices, and many other communications applications. By supporting leading substrate noise analysis EDA tools, TSMC is helping designers to bring these applications to market faster. Substrate models for TSMC’s advanced 0.13-micron mixed-signal process and its upcoming silicon germanium process are planned for later in the year.
In a mixed-signal design, fast digital blocks sometimes create unwanted “noise,” which may reach noise-sensitive analog portions of the chip, usually via a substrate – or silicon – path. The SeismIC? tool from Cadence and the SubstrateStorm? tool from Simplex create simulation models for the substrate of an IC. With this simulation model in hand, a designer can quickly and easily try different layout and isolation techniques to minimize contamination of noise-sensitive blocks.
“SoC devices with a mix of analog and digital circuitry are finding their way into wireless systems, networking, multimedia and other popular applications,” said Andrew Moore, Design Services Marketing manager at TSMC. “By providing our substrate data to these EDA companies, designers will have another means to automate the design of PLLs, filters, and other critical mixed-signal and RF blocks.”
TSMC has already extended its design services offerings by providing process data access to several developers of analog synthesis tools. In addition, TSMC recently announced several new Process Design Kits for mixed-signal processes.
To implement the new substrate analysis capability, designers must obtain encrypted technology files for the TSMC to 0.18-micron and 0.25-micron mixed-signal processes from Simplex and Cadence. These technology files are available today and have been software-validated against industry-standard process-characterization tools. Technology files for TSMC’s advanced 0.13-micron mixed-signal process and its upcoming silicon germanium process are expected to be available later in the year.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry’s leading process technology, library and IP options and other leading-edge foundry services. TSMC operates two six-inch wafer fabs and six eight-inch wafer fabs. The Company also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and WaferTech. In 2000, TSMC produced the foundry industry's first 300mm customer wafers and began constructing two dedicated 300mm fabs. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. More information about TSMC is available through the World Wide Web at http://www.tsmc.com.