WILSONVILLE, Ore. and HSINCHU, Taiwan – June 4, 2007 – Mentor Graphics Corporation (Nasdaq: MENT) and Taiwan Semiconductor Manufacturing Company, Ltd. (TSE:2330, NYSE:TSM) today announced that Mentor's design-for-manufacturing (DFM) and design-for-test (DFT) tools have been incorporated into TSMC Reference Flow 8.0. The new Reference Flow 8.0 features statistical timing analysis for intra-die variation, automated DFM hot-spot fixing and new dynamic low-power design methodologies.
Reference Flow 8.0 will include Mentor tools for critical area analysis and reduction, planarity (CMP) analysis and layer planarity control using smart fill algorithms, litho-friendly design, process variability aware analysis, and DFT flows based on Mentor Graphics Calibre® and TestKompress® solutions.
"Mentor is pleased to have the opportunity to again demonstrate the production worthiness of our DFM and DFT solutions at the world's premier dedicated semiconductor foundry," said Joe Sawicki, vice president and general manager, Design to Silicon Division, Mentor Graphics. "Our continued collaboration with TSMC will help designers address the challenges of nanometer semiconductor design and manufacturing."
"We believe Mentor Graphics DFM tools will further expand the confidence of designers who have been using Calibre for physical verification signoff," said Kuo Wu, deputy director of design service marketing at TSMC. "Mentor Graphics DFM tools are interoperable with Reference Flow 8.0 design tools, enabling them to fit easily into our customers' flows."
Documentation on Reference Flow 8.0 and qualified Mentor Graphics tools is available by contacting any TSMC account manager.
About the Mentor Graphics DFM Platform
Calibre LFD™ (Litho-Friendly Design) accurately models the impact of lithographic processes on "as-drawn" layout data to determine the actual "as-built" dimensions of fabricated gates and metal interconnects. Calibre LFD identifies layout "hot spots," structures with a higher probability of failing due to litho process variations, and grades them to determine which have the highest potential for yield improvement. Integration with Sierra Design Automation's Olympus-SOC™ design tools enables feed forward of Calibre LFD results to give designers guidance on recommended layout improvements, and to enable revalidation of correct timing after modifications.
Calibre Yield Analyzer performs critical area analysis (CAA) on all base and interconnect layers to identify areas of a layout with excess vulnerability to random particle defects, such as shorts and opens, due to close spacing of layout features. YieldAnalyzer provides guidance to help the designer quickly locate hot spots and determine what layout changes will result in the greatest yield improvement. This data is forward annotated to P&R tools like Sierra Olympus-SOC automatically reducing the critical area while ensuring that correct timing is preserved. Calibre YieldEnhancer™ automatically specifies a variety of interconnect and base layer enhancements such as via doubling, via enclosure expansion and general edge moving to improve yield. Modifications are fully back annotated to GDSII, OASIS™, LEF/DEF, OpenAccess™ and Milky Way™ design databases.
The Calibre CMP solution is integrated with TSMC's VCMP simulator, enabling the designer to model the CMP process and automatically add fill to the layout based on layout density, gradient and magnitude assessments. This intelligent "model-based fill" approach provides optimum planarity improvement to reduce bridging due to dishing and thickness variations, while minimizing added parasitic capacitance and its impact on timing. Calibre extraction tools, xRC and xL, also integrate with VCMP to create a comprehensive 3D circuit model with device and interconnect parameters that more closely match silicon results. The results can drive extremely accurate simulations using Mentor's ADiT™ or other leading circuit simulators supported by Calibre's back annotation facilities.
DFT capabilities based on Mentor Graphics TestKompress, MBISTArchitect™, and YieldAssist™ products, which have been part of TSMC's reference flow since version 6, continue to include both logic and memory testing. New facilities in Reference Flow 8.0 include power reporting during ATPG (automatic test program generation) for addressing test-specific power issues, and timing-aware ATPG features for targeting small delay defects.
About Mentor Graphics
Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of over $800 million and employs approximately 4,250 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven libraries, IP, design tools and reference flows. The Company's total managed capacity in 2006 exceeded seven million (8-inch equivalent) wafers, including capacity from two advanced 12-inch GigaFabs, four eight-inch fabs, one six-inch fab, as well as TSMC's wholly owned subsidiaries, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. TSMC is the first foundry to provide 65nm production capabilities. Its corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please visit http://www.tsmc.com.