Synopsys and TSMC Introduce First DesignWare Standard Cell Libraries

SANTA CLARA, Calif.--(BUSINESS WIRE)--March 20, 2000--As Part of its DesignWare Commodity IP Library, Synopsys Will Distribute and Support Silicon Libraries Optimized for TSMC's 0.15 and 0.13 Micron Processes

Synopsys, Inc., (Nasdaq:SNPS) the technology leader for complex integrated circuit (IC) design, and TSMC announced today at the IP2000 Conference a multi-year agreement to develop and optimize the Synopsys DesignWare(R) Standard Cell Silicon Library for TSMC's 0.15- and 0.13-micron advanced process technologies. The components will be added to Synopsys' extensive DesignWare library of commodity intellectual property (IP), and distributed and supported by Synopsys at no additional charge to DesignWare's current 15,000 customers worldwide.

To take full advantage of the latest electronic design automation (EDA) tools and silicon processes, IC designers require a complete IP library solution. The DesignWare silicon library provides all the necessary data views to support the leading front- and back-end design tools. It contains more than 600 standard cells, including gated-clock cells for Power Compiler(TM) and datapath cells for Module Compiler(TM), I/O cells and ProMA memory generators for RAM, ROM and register files.

"Combining Synopsys' silicon library and extensive EDA tool and flow expertise with TSMC's process technology expertise will allow IC designers to quickly take full advantage of the latest silicon processes," said F.C. Tseng, president of TSMC. "The libraries will be optimized to yield fast, small and low-power designs in TSMC silicon when designers use industry-standard design tools like Design Compiler, Physical Compiler, Module Compiler and Power Compiler."

"We're pleased to be working closely with TSMC, the world's largest silicon foundry, to provide the IP building blocks that allow designers to achieve the productivity required for system-on-a-chip (SoC) design," said John Chilton, vice president and general manager of Synopsys' Design Reuse Group. "This relationship underscores TSMC's recognition of our solid track record in delivering the highest-quality silicon libraries optimized for the industry's leading design and verification tools."

"As one offering in Synopsys' broad range of industry-leading EDA tools, DesignWare is part of the IC designer's standard desktop," said Kurt Wolf, TSMC's director of marketing. "By adding our jointly developed silicon libraries to DesignWare, IC designers have unmatched access to this high performance and easy to use method for implementing their designs in TSMC silicon."

As Synopsys continues to grow the DesignWare library, Synopsys and TSMC will validate each of the new complex commodity macrocells (such as MPEG2 video decoder, PCI-X and USB2.0 device) in TSMC's advanced silicon processes, ensuring that process, silicon library and macrocells work together optimally.

Pricing and Availability

The DesignWare 0.15-micron TSMC silicon library will be available in limited production in the second calendar quarter of 2000, and 0.13 micron available concurrently with TSMC's process introduction at no additional charge to current DesignWare customers.

About DesignWare Silicon Library

High-quality silicon libraries, tightly integrated with leading-edge tools tested in today's design flows and verified in silicon, enable customers to focus on design priorities rather than qualifying and validating libraries. The DesignWare Silicon Library consists of standard and special-purpose cells, datapath cells, an I/O pad library and memory generators. DesignWare adheres to best-in-class industry design practices for deep submicron design, including requirements for highest density, maximum performance and low power.

In addition to the silicon libraries, the DesignWare library co