HSIN-CHU, Taiwan, November 14, 2000 - Taiwan Semiconductor Manufacturing Company (NYSE: TSM), the world’s largest dedicated semiconductor foundry, today announced the development of the industry’s first comprehensive 0.13-micron, mixed-signal/radio-frequency (RF) test chip. The new test chip will help TSMC to create characterization reports, and other elements of the 0.13-micron, mixed-signal/RF design kit. This kit will be delivered in time for design starts.
The mixed-signal/RF, 0.13-micron geometry will enter production in the fourth quarter of 2001, and will enable companies to achieve higher frequencies at a lower cost and to accommodate higher levels of complexity in a smaller space for system-on-chip (SOC) RF designs. The test chip will aid companies in the acceleration of higher bandwidth designs, including Bluetooth and SONET-based communications and consumer products.
The RF test chip includes functional cells for voltage-controlled oscillator (VCO), low noise amplifier (LNA), high Q inductor, RF MOS and transformer and transmission lines. These cells will be used in cellular phone, Bluetooth, 802.11 and home RF designs.
With the announcement of this next-generation 0.13-micron mixed-signal/RF test chip, TSMC is providing the RF and mixed-mode design communities with a new level of design planning capability. TSMC’s goal is to meet the broad range of design requirements at the 0.13-micron technology level, and with this platform, TSMC has illustrated it is on the forefront of meeting customers’ validation needs for high-frequency SOC designs.
“Our 0.13-micron, mixed-signal/RF test chip targets the industry’s most advanced communications designs,” said David Sheng, director of advanced technology product marketing at TSMC. “The new test chip and design kit take the guesswork out of the design process. This increases the chances for right-the-first-time design success and shrinks the concept-to-silicon cycle dramatically.”
About TSMC’s 0.13-Micron Mixed-Signal/RF Process
TSMC’s 0.13-micron mixed-signal/RF process represents an aggressive advancement in the company’s industry-leading mixed-signal/RF roadmap, which began with the 0.25-micron generation. The processes are fully compatible with TSMC’s industry-leading 0.13-micron process, and feature a core voltage of 1.2 volts and an I/O voltage of 2.5 or 3.3 volts.
Designers can add 1.2 volt, 2.5 volt or 1.2 volt, 3.3 volt transistors for mixed-signal cores and I/Os; precision capacitors and resistors for high-performance mixed-signal functions; and high-quality inductors, varactors and diodes for RF functions. The optimized process has an N-channel MOS (NMOS) device with a cut-off frequency (fT) much higher than 80 GHz, and a maximum frequency (fmax) much higher than 60 GHz? which is very attractive in high-frequency, mixed-signal and RF designs.
About TSMC’s 0.13-Micron Process
TSMC’s advanced 0.13-micron process delivers the foundry industry’s most advanced technology for high-performance, high-density system-on-chip (SOC) designs. The process features a complete technology family, including core, high-performance, ultra-high-speed, low-power and mixed-signal offerings. TSMC’s 0.13-micron process can use up to eight layers of copper interconnect, as well as low k dielectric material.
Built to TSMC’s industry-leading standards for quality and reliability, the 0.13-micron process provides a 72 percent shrink versus TSMC’s popular 0.18-micron technology, enabling more logic density per square millimeter for system-level integration with the highest possible performance. The process supports all TSMC technology offerings, including logic, embedded SRAM, embedded flash, and mixed signal technologies.
About TSMC’s 0.13-Micron Design Kit <