HSIN-CHU, Taiwan, June 3, 2002 - Taiwan Semiconductor Manufacturing Company (TSMC) today announced Reference Flow Release 3.0, the foundry industry's first design methodology with a true hierarchical approach to high-gate-count design.
TSMC's Reference Flow 3.0 uses best-of-class tools from key electronic design automation (EDA) vendors to support a "divide and conquer" approach to complex system-on-chip (SoC) design at both the logical and physical implementation stages. Designers and design teams can use this comprehensive, hierarchical approach to focus on sub-blocks of the overall design, independently of each other, with confidence that the final integration can be accomplished smoothly. This makes it easier for designers to take full advantage of TSMC's advanced process technologies, integrating more functionality into a single chip.
Previously, TSMC's Reference Flow ensured manufacturability of the design in TSMC silicon. While this goal is still paramount, TSMC Reference Flow 3.0 raises the bar by addressing system-on-chip design challenges, particularly those relating to routing at the 0.13-micron and below process nodes.
TSMC's new flow features several key enhancements, including virtual prototyping, partitioning and modeling, deep-submicron routing for manufacturability, and extended RC and delay correlation. In addition, the new flow addresses flip-chip design and includes a memory built-in-self-test (BIST) integration capability.
"With Reference Flow Release 3.0, designers can now address complex SoCs the way they should be addressed - heirarchically, in a design team approach, integrating the final product at the back end of the design cycle,"said Dr. Ping Yang, vice president of R&D for TSMC. "This is essential for sub-130 nanometer designs, where blocks are very large and functionally complex, and where gate counts of three million or more are routine."
Reference Flow 3.0 contains several key features to enable the hierarchical physical implementation, including "Virtual Prototyping," deep sub-micron routing, and modeling. In addition, the flow also includes the enhanced and newly added features of RC and delay correlation and flip-chip implementation
Reference Flow 3.0 users can generate a "virtual prototype" of the final design that verifies physical characteristics such as timing, routability, IR drop, and floor plan. The design is then partitioned into functional blocks for pin assignment and timing budgeting. With virtual prototyping, designers can make logic changes as necessary and conduct physical synthesis, clock tree synthesis, placement and routing at the block level, with greater assurance that the final, integrated design will function as planned.
Deep Submicron Routing for Manufacturability
Reference Flow Release 3.0 helps designers achieve optimum routing through consistency checks for TSMC process specific design rules, including multiple wire spacing rules, double via rules, antenna rules. In addition, the improved routing techniques help minimize the need for special metal slotting and reduce crosstalk effects.
Modeling for Hierarchical Block Integration.
Accurate and efficient modeling for clock, timing and antenna requires hierarchical block integration at the top level. TSMC Reference Flow Release 3.0 provides antenna modeling flow enhancements that accurately handle the sub-blocks in a hierarchical physical design.
Comprehensive RC and Delay Correlation
Comprehensive RC and Delay Correlation has been a main focus of the TSMC Reference Flow for both implementation execution efficiency and manufacturability. Release 3.0 adds well-correlated technology files based on TSMC's 0.13-micron library.
The files are calibrated to TSMC silicon. T