San Jose, CA— March 21, 2001 –Cadence Design Systems, Inc., the world's largest EDA solutions provider and a leading provider of signal integrity tools, announced today that Taiwan Semiconductor Manufacturing Company (TSMC), the world's largest dedicated semiconductor foundry, will provide data for technology files for SeismIC, Cadence’s substrate noise analysis tool. These technology files will enable designers of mixed-signal chips to analyze substrate noise effects prior to tape-out to TSMC’s industry-leading 0.18-micron and 0.25-micron logic and mixed signal processes.
“SeismIC provided valuable information regarding sources of substrate noise for our DAC converter. We are convinced that SeismIC will be a critical part of our methodology for successfully integrating analog and digital components on our chips. Having TSMC technology files will speed up our ability to use SeismIC,” said Dr. Toshi Hamasaki, general manager of R&D at TI, formerly Burr-Brown.
"Communications IC designers are increasingly concerned about substrate noise," said Mike Pawlik, VP of Corporate Marketing at TSMC. "By sharing our process data with select EDA leaders in this area, we can help them extend their substrate analysis capabilities. This is yet another milestone in our mixed-signal partnership with Cadence, closely following our recent Process Design Kit collaboration.”
“TSMC and Cadence recognize that substrate noise is a critical design issue. Cadence is pleased to work with TSMC, the world’s leading foundry, to provide designers with a powerful analysis capability to deal with substrate noise ,” said Charlie Huang, VP of R&D at Cadence.”
After initial calibration efforts, TSMC has released data for SeismIC technology files for TSMC’s 0.18-micron and 0.25-micron mixed-mode processes. The availability of these technology files, combined with the recently released TSMC Process Design Kits (PDKs) for Cadence tools, will provide a key advantage to mixed-signal designers who utilize TSMC’s leading process technologies.
SeismIC performs substrate RC model extraction, noise simulation and advises on techniques to minimize substrate noise. SeismIC’s extraction and simulation engines facilitate design verification, trade-off analysis and optimal noise immune designs. SeismIC can presently handle CMOS, epi-CMOS, BiCMOS and SiGe processes.
About TI/Burr-Brown Japan
Texas Instruments Incorporated is a global semiconductor company and the world's leading designer and supplier of digital signal processing and analog technologies, the engines driving the digitization of electronics.
Texas Instruments Incorporated is a leader in the real-time technologies that help people communicate. We are movingfast to drive the Internet era forward with semiconductor solutions for large markets such as digital wireless and broadband access.
About Cadence Design Systems , Inc
Cadence is the largest supplier of electronic design automation products, methodology services, and design services used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,400 employees and 2000 revenues of approximately $1.3 billion, Cadence has sales offices, design centers, and research facilities around the world. The Company is headquartered in San Jose, Calif. and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services may be obtained from the World Wide Web at www.cadence.com.
TSMC is the world's largest dedicated semiconductor foundry, providing the industry’s leading process technology, library and IP optio