Hsinchu, Taiwan, March 16, 2000 - Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM) today announced that it has introduced the pure-play foundry industry's first 0.15 micron process and delivered the first 0.15 micron wafers to Altera Corporation with yields comparable to current 0.18-micron process technology. The new technology reduces die size by 26 percent and provides performance improvements between 25 to 30 percent over the same device on TSMC's leading 0.18-micron process technology. When compared to TSMC's high-volume 0.25-micron process, the new 0.15-micron process results in less than half the die size and nearly twice the performance.
The 0.15-micron process was qualified at TSMC Fab 3 and will be deployed in three additional TSMC fabs by the end of 2001. In addition to Altera, TSMC has accepted 0.15-micron tapeouts from three other undisclosed customers and is expecting four additional customer tapeouts within the next month. Production has begun and is expected to accelerate to high volume in the third quarter of this year.
"This is an exciting development and a remarkable time for Altera and TSMC," said Francois Gregoire, senior director of technology for Altera Corporation. "Not only has TSMC delivered to us the foundry industry's first 0.15-micron technology, but they have done so with excellent yields and excellent device performance. As a technology driver, we are actively working with TSMC to extend their 0.15-micron technology development program with a copper interconnect alternative. Within two months, we will receive from TSMC the first 100 percent copper chip at the 0.15 micron generation, that will give us a good understanding of the benefits of copper which will be used for all our products on 0.15-micron and 0.13-micron processes."
About the Technology
The 0.15-micron technology family will include baseline, low voltage, and low power processes. The first baseline and low-voltage processes are beginning production now, while the low-power process will begin production in the third quarter of 2000.
TSMC's 0.15-micron technology employs seven layers of metal and has an L-effective gate length of 0.11 micron. Gate delay is 16 picoseconds for the low-voltage version with gate overdrive and as low as 14 picoseconds for a special, CPU-targeted process option. Features include 1.2V and 1.5V core options and I/Os from 2.5 to 3.3V.
The technology's 6T SRAM cell size is 3.42um2 , the smallest in the industry. This enables use of up to 16M of SRAM on a single die, making the technology ideal for a variety of system-on-chip (SOC) applications in the networking, computing and consumer market segments.
TSMC has already received an extensive array of 0.15-micron libraries, such as core cells, memory compilers and I/O cells, from the industry's leading library vendors, including Artisan Components, Avant!, Nurlogic, Synopsys, and Virage Logic.