SAN JOSE, Calif., October 28, 2002 - Taiwan Semiconductor Manufacturing Company, Ltd. [(TSMC) (TAIEX: 2330, NYSE: TSM)], the leader in semiconductor foundry technology, and Synopsys, Inc. (Nasdaq:SNPS), the leader in complex integrated circuit (IC) design, have qualified Synopsys’ signal integrity (SI) suite to address the design methodology for 130 nanometer (nm) and 90 nm process technologies. This extension of design methodology is the result of an ongoing collaboration to utilize the latest silicon processes. This is the first IC industry collaboration delivering a comprehensive SI suite for 130 nm and 90 nm processes.
“Over the last several years, TSMC and Synopsys have proactively worked together to provide methodologies for complex design challenges,” said Genda Hu, vice president of Marketing at TSMC. “Both companies have a firm grasp on the signal integrity issues at the 130 nanometer node and beyond. Synopsys has created the first credible pre-silicon result, based on the requirement to provide our customers with the ability to prevent or quickly analyze and repair their complex signal integrity issues.”
Signal Integrity Challenges
With process geometries shrinking and frequency requirements dramatically increasing, one of the biggest challenges for system-on-chip (SoC) design teams is ensuring timing and signal integrity closure. The critical signal integrity issues include crosstalk delay, noise, and IR drop. Considering these effects during design implementation reduces the risk of design failure in silicon or unmet performance specifications.
TSMC and Synopsys have proactively addressed SI issues by deploying a proven methodology using Synopsys’ industry-leading IC implementation and analysis tools coupled with TSMC’s manufacturing expertise. The upcoming TSMC Reference Flow 4.0 will incorporate a number of Synopsys’ tools, including Astro™ , Astro-Rail™ , Astro-Xtalk™ , Design Compiler™ , Floorplan Compiler™ , Physical Compiler™ , PrimeTime®, PrimeTime® SI, and Star-RCXT™ .
“TSMC’s advanced process technologies enable their customers to lead the way in complex system design and drive some of the most advanced flow requirements,” said Deirdre Hanford, senior vice president of Synopsys’ Business Market Development Group. “This important milestone is the result of an ongoing collaboration between Synopsys and TSMC that focuses on increasing our mutual customers’ efficiency and lowering their project risk.”
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, seven eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nanometer-micron technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan. For more information about TSMC please go to http://www.tsmc.com.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
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Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Astro, Astro-Xtalk, Astro-Rail, Design Compiler, Floorplan Compiler, Physical Compiler, and Star-RCXT are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.