TSMC Introduces Foundry Industry's First Comprehensive DFM Toolkits

SAN JOSE, CA – June 9, 2005 -- Taiwan Semiconductor Manufacturing Company (TSE: 2330, NYSE: TSM), today unveiled two new comprehensive and powerful DFM (Design For Manufacturing) Toolkits that improve product yield, increase device performance and enhance semiconductor companies’ return on design investment. These process-based toolkits, Yield Plus and Yield Pro, allow designers to build on their best efforts, to generate even greater returns to the bottom line. Based on a wealth of accumulated process data, the new DFM Toolkits drive TSMC process-specific capabilities into electronic design automation (EDA) tools from key suppliers, and include a number of unique TSMC-provided services. “TSMC extends its foundry leadership by defining two DFM toolkits that improve yield, performance and ROI,” said Ed Wan, senior director of design service marketing for TSMC. These toolkits are the technology equivalent to having the best caddie on the golf course at your side every time you play. Yield Plus, developed by TSMC and its EDA partners and implemented at the designer's discretion, includes Action-Required rules, Recommended Advisories and Guidelines for semiconductor design. Also included are DFM utilities to implement the rules and advisories. Yield Pro includes several unique services that are implemented by TSMC at the manufacturing stage to quickly move a design into volume production. Yield Pro Services include a Lithography Process Check (LPC) Service, a Yield Sensitivity Analysis (YSA) Service; a Package Modeling Service; and sophisticated Scan Diagnostic services. Together, these services create a powerful methodology that increases yield at the design stage, and in early semiconductor manufacturing stages. This accelerates production ramps, enabling greater returns on dollars spent on design and manufacturing. TSMC's DFM toolkits are particularly important to the foundry's new 65nm Nexsys(SM) Technology for SoC Design, which is expected to enter risk production in 4Q2005. The 65nm Nexsys platform allows designers to build logic devices with double the density of the company's industry leading 90nm technology. This massive integration – the equivalent of more than 750 billion transistors on a single 12-inch wafer – enables significant cost savings to market movers across the IC industry. While TSMC's Reference Flows address design closure, TSMC's DFM toolkits use process-specific knowledge to improve upon designers’ best efforts without increasing die size. TSMC Reference Flow 6.0 also has partial coverage of DFM treatments such as metal density utility provided by TSMC and half-pitch wire spreading implemented by EDA vendors.

About TSMC

TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer fab. TSMC also has substantial capacity commitments at its wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint venture fab, SSMC. In early 2001, TSMC became the first IC manufacturer to announce a 90-nm technology alignment program with its customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For more information about TSMC please see http://www.tsmc.com.