HSIN-CHU, Taiwan, July 19, 1999- Taiwan Semiconductor Manufacturing Company (TSMC) (NYSE:TSM) today announced the industry's first dedicated Multiproject Wafer (MPW) processing service for 0.18-micron process technology. Called 0.18-micron MPW, the program offers a routinely scheduled multiproject wafer run to customers on a shared-cost basis for prototyping and verification. 0.18 MPW accelerates time-to-market for device designers and library and IP developers by reducing development mask and cutting wafer costs by up to a factor of ten.
TSMC developed its MPW program in response to today's system-on-chip (SOC) development methodologies, which often require the independent development, prototyping and validation of several cores before they can be integrated onto a single device. A complex SOC may require RISC, DSP, Ethernet and physical interface cores, each of which has to be verified individually before integration. By sharing resources with other TSMC customers, the SOC supplier can enjoy reduced prototyping costs and greater confidence that the design will be successful.
"To produce a successful system-on-chip, our customers and partners often spend enormous sums of money verifying each module within a given design. They can reduce this amount of investment by leveraging the MPW program," said PN Tseng, deputy director of advanced technology marketing at TSMC. "The MPW program is a proven vehicle for device, IP and library developers who must act concurrently when designing true multi-function single-chip systems. It is ideally suited for module-based design or chip prototyping and it enables designers to leverage a shared cost model."
Initially introduced in October 1998 for 0.25-micron process technology, TSMC's MPW program has been successfully used in over one hundred designs. With this announcement, TSMC has extended the MPW program to all customers and library and IP partners using its 0.18-micron process technology.
"The MPW program eliminates costly time-consuming mask and wafer iteration runs, resulting in accelerated time-to-market and an increase in customer profit margins," continued Tseng. "By extending the MPW program to include 0.18-micron processes, TSMC offers customers and partners a cost-efficient way to shorten design cycles despite increasing chip complexity."
0.18-micron MPW Tape-in Schedule
Design tape-in for TSMC's 0.18-micron logic MPW service is scheduled for September 20, 1999. Tape-out will follow one week after tape-in, and TSMC will provide parts to designers within two and a half months of initial tape-in. To sign up, designers and partners submit a request one week prior to the design tape-in date.
TSMC's 0.18-micron MPW service offers 1P6M dual-gate oxide logic (1.8V/3.3V). The basic block size is 200 mil x 200 mil. Up to 40 bare dice or ceramic packaged parts will be shipped with each run. Customers will pay for bare dice or packaged parts based on the number of basic blocks used and the cost of the packaging.
TSMC is the world's largest dedicated IC foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory, and BiCMOS chips. Currently, TSMC operates two six-inch wafer fabs (Fab 1 and 2) and three eight-inch wafer fabs (Fab 3, 4 and 5), all located in Hsin-Chu, Taiwan.
In addition, TSMC is delivering wafers from its first U.S. foundry, WaferTech, a joint venture with Altera, Analog Devices and Integrated Silicon Solutions, Inc. The company is currently executing plans to house Fabs 6 and 7 in the new Tainan Park, and expects first wafer outs in the first quarter of 2000. TSMC recently announced its participation in a $1.2 billion joint venture fab with Philips Semiconductor scheduled t