Custom-Touch 1T-SRAM Memory Compiler Development Launched for TSMC 0.18- and 0.15-Micron Standard Logic Processes

SUNNYVALE and FREMONT, Calif.--(BUSINESS WIRE)--Jan. 31, 2000--Fourth Generation Memory Compilers Broaden the Reach of Ultra-Dense Single Transistor SRAM

MoSys, Inc. and Virage Logic Corp. have established a partnership to develop fourth generation memory compilers based on MoSys' 1T-SRAM and Virage's Custom-Touch compiler technologies for TSMC's 0.18- and 0.15-micron standard logic processes.

These memory compilers are designed to enable system designers requiring ultra-dense memory to easily embed large quantities of cost-effective memory in their designs. By combining Virage's industry-leading Custom-Touch compiler technology with MoSys volume production-proven 1T-SRAM memory technology, customers will have the flexibility of rapidly generating the high-capacity memory instances of their choice at any stage of the design cycle. The compilers will facilitate "what-if-analysis" and performance trade-off decisions early on in the design cycle.

The Custom-Touch 1T-SRAM compilers will have a template generation mechanism for EDA (Electronic Design Automation) models that will empower users to freely choose from one of many popular design flows and ensure that all the necessary information is automatically generated for integrating and verifying the memories.

Additionally, Virage's compiler development process subjects all released products to rigorous testing as part of the company's FirstPass-Silicon program. For these compilers, TSMC will manufacture the test chips and Virage and MoSys will rigorously test and evaluate the Custom-Touch 1T-SRAM compiled instances in silicon. This will provide customers with a comprehensive silicon report, giving them additional confidence that their compiled memories will work in silicon.

"TSMC's deep submicron process give our customers the platform for their complex SOC products," said Roger Fisher, TSMC's senior director, corporate marketing. "Custom-Touch 1T-SRAM compilers for our leading 0.15 and 0.18-micron processes gives customers easy access to high capacity memory required in these designs." Availability of the first of these Custom-Touch 1T-SRAM compilers is scheduled for Q2, 2000.

"We are pleased to make Custom-Touch 1T-SRAM compilers available to TSMC customers" said Vin Ratford, Virage Logic's vice president of marketing and sales. "The MoSys-Virage partnership is committed to proliferating this unique memory technology to enhance productivity and enable system designers to make smart technical decisions without making any unnecessary compromises. For the first time, the performance benefits of SRAM and density advantages of DRAM can be combined in a compilable form". Memories built using the compiler will include the same yield-enhancing built-in sector redundancy proven in the volume production of 1T-SRAM devices. Compiled memory users can now build optimal designs without having to compromise between density, performance, and power.

"Custom-Touch 1T-SRAM compilers deliver the memory innovation and ease-of-use that TSMC's customers have come to expect from MoSys and Virage", stated Mark-Eric Jones, vice president and general manager of intellectual property at MoSys, Inc. "By working with TSMC to enable both their 0.18-micron and 0.15-micron customers, our partnership is facilitating the memory integration critical to the broader adoption of SoC methodology."

About 1T-SRAM

Available in densities up to 128Mbits, MoSys' patented 1T-SRAM technology uses a single transistor cell to achieve its exceptional density while maintaining the refresh-free interface and low latency random memory access cycle time associated with traditional six-transistor SRAM cells. Embedded 1T-SRAM allows designers to get beyond the density limits of six-transistor SRAMs; it also reduces much of the circuit complexity and e