December 7, 1999, Hsin-chu, Taiwan - Taiwan Semiconductor Manufacturing Company (NYSE: TSM) today becomes the first pure-play foundry to formally offer a commercially available 0.18-micron copper process. The advanced two-layer copper process was developed in TSMC's own R&D facility and is design-rule compatible with TSMC's baseline 0.18-micron process technology.
"The introduction of the foundry industry's first commercially available copper process opens the opportunity for all semiconductor companies to compete at the cutting edge of technology," said TSMC president FC Tseng. "Our customers will be ahead of the curve in applying copper's performance and reliability characteristics to the design of new products that will populate the technology landscape of the future."
TSMC's new copper process is implemented on the top two layers of the company's six-layer-metal, 0.18-micron CMOS process technology. The dual Damascene process features 1.6 times lower metal resistance than aluminum/tungsten metalization schemes. Other process benefits include an RC delay reduction of up to 15 percent, 30-to-50 times higher electromigration reliability, and a via series resistance that is five times lower than that of tungsten plug vias. In addition, competitive analysis reveals TSMC's design rules to be tighter than those of competing technologies, indicating that design density should also be higher.
Current semiconductor technology employs an aluminum/tungsten metalization system. Copper presents lower electrical resistance than the aluminum/tungsten schemes, improving performance by reducing the interconnect delays seen in many integrated circuits. In addition, the lower resistance of the copper process allows power to be distributed across an IC, more effectively enabling improved device performance throughout the chip. This is especially important for low power and high-density devices, where resistance can cause a loss of power - due to IR drops.
TSMC's roadmap calls for multiple generations of copper processes in two layers, with optional all-layer copper production at any time. The company has already begun development of a 0.15-micron copper process and a 0.13-micron copper process. This makes TSMC's copper process an excellent vehicle for migrating new semiconductor products through multiple generations of process technology.
The 0.18-micron copper process will be released to production initially in the company's 8-inch fabs in Hsin-Chu Science-Based Park, Taiwan, with full production expected to include Fab 6, located in Taiwan's new Tainan Science-Based Park. Fab 6 is currently installing its process equipment.
Because TSMC's two-layer copper process is design rule compatible with the company's existing 0.18-micron CMOS process, it requires no special library, IP or EDA design tool support.
"By offering copper on the top two layers, we are addressing the most immediate performance and reliability concerns of our performance-driven customers," said Mike Pawlik, vice president of marketing for TSMC. "We have also processed a number of all-layer copper wafers and expect them to provide even greater benefits, particularly at smaller geometries."
TSMC is accepting tapeouts for products utilizing the 0.18-micron copper process in two layers or all layers. The new 0.18-micron copper process is a part of the company's turnkey technology offering that includes process, design service, testing, and customer support.