TSMC Debuts 0.25 Micron Silicon IP Program and Partners

San Jose, CA., June 17, 1998- Taiwan Semiconductor Manufacturing Company (TSMC) today announced the TSMC Silicon IP (TSMC Si IP) Program, the company's silicon verification test chip program for library, IP, and EDA vendors. The purpose of the program is to provide our partners with slots for their own test chips on leading-edge technology mask and wafer lots. Chips from these wafers are delivered back to each vendor for their own analysis. These wafer lots will be run regularly by TSMC.

The company further announced that it has, to date, solidified TSMC Si IP partnerships with fourteen vendors. TSMC is now making 0.25um CMOS wafers incorporating these vendors' test chips. Test chip results and data will be available for customers in the second half of 1998.

Partner vendors are Artisan Components, Aspec Technology, Avant!, Duet Technologies, Galax!, IMS, Leda Systems, Mentor Graphics, NurLogic Design, Silicon Access, Silicon Architects of Synopsys, Simplex Solutions, Virage Logic , and Virtual Silicon Technology.

"TSMC's objective with this program is to facilitate the early verification of our partners' products in TSMC technology, and provide our customers with the data and predictability they need to complete their design and meet their market window," commented Ron Norris, TSMC, USA president. "We recognize that each partner has a unique offering and, together, they provide a broad range of solutions to meet our customers' individual needs".

About TSMC

TSMC (ADS traded NYSE: TSM, also traded on TSE) is the world's largest dedicated integrated circuit ("IC") foundry and offers a comprehensive set of IC fabrication processes, including processes to manufacture CMOS logic, mixed-mode, volatile and non-volatile memory and BiCMOS chips. Currently, TSMC operates two 6-inch wafer fabs (Fab1 and 2), and three 8-inch wafer fabs (Fab 3,4 and 5), all located in Hsin-Chu, Taiwan. In mid-1996, TSMC commenced construction on its first U.S. foundry, WaferTech - a $1.2 billion joint venture with Altera, Analog Devices and Integrated Silicon Solutions, Inc. Production at WaferTech is scheduled to commence in 1998. The company plans to spend approximately NT$98.5 billion(US$3.5 billion) during the period from 1997 through 1999 for bringing Fabs 3,4 and 5 into full production and the construction of Fabs 6, and 7 are expected to be located in the new Tainan Park. Corporate headquarters are in Taiwan. For further information: http://www.tsmc.com.